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31. 发明专利

JPH10161688A SURROUND CIRCUIT 失效
公开(公告)号：JPH10161688A
公开(公告)日：1998-06-19
申请号：JP32035696
申请日：1996-11-29
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H04S1/00 , G10K15/12 , H03M1/00
摘要： PROBLEM TO BE SOLVED: To provide a surround circuit in which the number of D/A converting circuits is reduced by use of an A/D converting circuit, a delay circuit and a D/A converting circuit. SOLUTION: An input signal is smoothed after full-wave shaped by a full wave shaping circuit 15, and the output frequency of a VCO 18 is changed by the smoothing result. The input signal of an input terminal IN is digitally converted by the sampling signal of the VCO 18 in an A/D converting circuit 11. The output signal of the A/D converting circuit 11 is delayed by a memory 12, and then converted into an analog signal by the sampling signal in a D/A converting circuit 13. Since the frequency of the sampling signal is changed while the output signal of the A/D converting circuit 11 is stored in the memory 12, the sampling frequencies of the A/D converting circuit 11 and the D/A converting circuit 13 are mutually differed to the same data. Therefore, the frequency of the input signal can be relatively faded to falsely reproduce the surround.

32. 发明专利

JPH0784870A STORAGE CIRCUIT 失效
公开(公告)号：JPH0784870A
公开(公告)日：1995-03-31
申请号：JP18909493
申请日：1993-06-30
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO , YAMADA SUSUMU
IPC分类号： G06F12/06 , G11C7/16 , G11C8/04 , G11C8/12 , G06F1/06 , G10K15/12
摘要： PURPOSE:To easily obtain data on plural delay times. CONSTITUTION:A data input part 32 writes data in a memory 30 in order. A data output part 36 outputs data from eight areas (a)-(f) of the memory 30 in parallel. Then SW1 and SW2 select and output read data from the eight areas (a)-(f) of the memory 30 in order. The respective output data can be stored in different locations of the memory by shifting the read position by the SW1 and SW2. Consequently, plural data which are different in write and read time difference (different in delay time) can be obtained at the same time.

33. 发明专利

JPH0738435A DELAY CIRCUIT 失效
公开(公告)号：JPH0738435A
公开(公告)日：1995-02-07
申请号：JP17951593
申请日：1993-07-21
申请人： SANYO ELECTRIC CO
发明人： ISHIKAWA TSUTOMU , MEYA MASATO
IPC分类号： G10K15/12 , H03M1/00 , H03M1/52 , H04M3/00 , H04S7/00
摘要： PURPOSE:To make a time constant of a variable integration circuit of an A/D converter coincident with that of a D/A converter. CONSTITUTION:An adder circuit 20, a quantization circuit 22 and a variable integration circuit 24 make A/D conversion and the result is stored in a memory 12. Then the time constant of the variable integration circuit is controlled by a control circuit 26. On the other hand, data from the memory are integrated by a variable integration circuit 28 to obtain an analog signal. In this case, control data from the control circuit 26 are sent to a control circuit 34 via a memory 32 and the control circuit 34 uses control data to be sent to control a time constant of the variable integration circuit 28.

34. 发明专利

JPH04291818A OSCILLATION CONTROL CIRCUIT 失效
公开(公告)号：JPH04291818A
公开(公告)日：1992-10-15
申请号：JP5718891
申请日：1991-03-20
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H03L3/00
摘要： PURPOSE:To accurately control the oscillation by forming a frequency divider circuit frequency-dividing the output of an oscillation circuit with a flip-flop circuit and resetting it with a control signal. CONSTITUTION:Frequency divider circuit 8 is formed with D flip-flop circuits 9-12 connected in cascade. Each of the flip-flop circuits 9-12 is reset in response to a control signal from a control circuit 3. Suppose that a power supply 2 is applied to the control circuit 3 with the closing/opening of a switch 1 and an instantaneous pulse is generated from the control circuit 3, an oscillator 6 starts the operation and the reset of the flip-flop circuits 9-12 is momentarily released and the oscillation output from the oscillator 6 starts being frequency- divided by the flip-flop 9 or the like. However, so long as the width of the instantaneous pulse is less than 8 periods of the oscillation clock from the oscillator 6, before the oscillation output signal is outputted from an output terminal 13, resetting is applied again to the flip-flop circuits 9-12. Thus, the oscillation is responded to the control signal accurately without malfunction due to switching.

35. 发明专利

JPH04167800A BALANCE ADJUSTMENT CIRCUIT 失效
公开(公告)号：JPH04167800A
公开(公告)日：1992-06-15
申请号：JP29436990
申请日：1990-10-30
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H04S7/00
摘要： PURPOSE:To prevent the generation of a shock sound by controlling the amount of adjustment so as to gradually reduce the amount of adjustment to zero at the time of non-adjustment. CONSTITUTION:A direction discriminating circuit 20 discriminates whether or not the counting value of a counting circuit 19 is up or down direction to the initial value (non-control state data), the opposite direction of the direction at that time, that is, an updown signal in the direction returning the counting value of the counting circuit 19 to the initial value is applied to a switch 21. As the result, the counting circuit 19 returns to the initial value gradually, a decoder 23 makes the amount of decay of left and right attenuating circuits 12 and 13 to the same value accompanied by it. Thus, the shock sound can be prevented because of the gradual attenuation.

36. 发明专利

JPH04162900A BALANCE ADJUSTMENT DEVICE 失效
公开(公告)号：JPH04162900A
公开(公告)日：1992-06-08
申请号：JP28923690
申请日：1990-10-26
申请人： SANYO ELECTRIC CO
发明人： ISHIKAWA TSUTOMU , MEYA MASATO
IPC分类号： H04S7/00
摘要： PURPOSE:To avoid an event that 2nd balance adjustment may take much time when a test signal generator is once selected and released again by storing the adjustment value of a balance adjustment circuit in a register while a test signal is applied and the stored adjustment value is returned to the balance adjustment circuit after the end of the period. CONSTITUTION:The adjustment device is provided with a 2nd register 9 built in a balance adjustment circuit 6 and storing the adjustment value in response to the level difference of a left and right stereo signal, a 1st register 10 storing the data stored in the 2nd register 9 during the application of the test signal, and a detection circuit 11 waveform-shaping a switching control signal from a control terminal 14. In this case, when a test signal period is finished and the signal falls down, the trailing is detected by a trailing edge detection circuit 13 and fed to a clock terminal of the 2nd register 9, the 2nd register 9 fetches the data of the 1st register 10. Since the data is the same as that stored in the 2nd register 9 just before the test signal period, the adjustment is immediately executed when the left/right stereo signal is applied.

37. 发明专利

JPH0461600A BALANCE ADJUSTMENT CIRCUIT 失效
公开(公告)号：JPH0461600A
公开(公告)日：1992-02-27
申请号：JP17338390
申请日：1990-06-29
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H04S7/00 , H03G3/20 , H03G3/30
摘要： PURPOSE:To attain automatic balance adjustment by applying a timing signal to an oscillation circuit via a gate means and controlling a comparate size of a window comparator with the output of an end detection circuit. CONSTITUTION:A timing signal generating circuit 16 consists of a window comparator having an inverter at its output terminal and applies an output signal of an L level to an AND gate 24 when an output signal V1 of a signal generating circuit 15 is in the relation of V1>VD and V1

38. 发明专利

JP2009044248A Y/c separation circuit 审中-公开
标题翻译： Y / C分离电路
公开(公告)号：JP2009044248A
公开(公告)日：2009-02-26
申请号：JP2007204528
申请日：2007-08-06
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , ISHII SATOYUKI , SERIZAWA SHUNSUKE
IPC分类号： H04N9/78
摘要： PROBLEM TO BE SOLVED: To extract a brightness signal and a chroma signal appropriately from a video signal without requiring an A/D converter. SOLUTION: The Y/C separation circuit comprises a first switched capacitor filter combining the vertical high-pass filter function and the horizontal low-pass filter function, a second switched capacitor filter having the vertical low-pass filter function, a brightness signal generation section for extracting the brightness signal included in a video signal by superimposing the outputs from the first and second switched capacitor filters, and a third switched capacitor filter having the vertical high-pass filter function and the horizontal high-pass filter function and extracting the chroma signal by superimposing the outputs from the vertical high-pass filter function and the horizontal high-pass filter function. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：从视频信号中适当地提取亮度信号和色度信号，而不需要A / D转换器。解决方案：Y / C分离电路包括组合垂直高通滤波器功能和水平低通滤波功能的第一开关电容滤波器，具有垂直低通滤波器功能的第二开关电容滤波器，亮度信号产生部分，用于通过叠加来自第一和第二开关电容滤波器的输出来提取包括在视频信号中的亮度信号，以及具有垂直高通滤波器功能和水平高通滤波器功能的第三开关电容滤波器，以及提取通过叠加来自垂直高通滤波器功能的输出和水平高通滤波器功能的色度信号。版权所有（C）2009，JPO＆INPIT

39. 发明专利

JP2007103691A Electrical circuit including direct charge switched capacitor circuit 有权
标题翻译：包括直接充电开关电容器电路的电路
公开(公告)号：JP2007103691A
公开(公告)日：2007-04-19
申请号：JP2005291934
申请日：2005-10-05
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： MEYA MASATO , SERIZAWA SHUNSUKE
IPC分类号： H01L21/822 , H01L27/04 , H03K5/08
摘要： PROBLEM TO BE SOLVED: To suppress the influence of parasitic capacitance in a switched capacitor circuit.
SOLUTION: An electrical circuit is equipped with at least one of memory units 52 which contain switching elements Toa, Tia, Tob, and Tib and are capable of selecting either a first mode or a second mode. In the first mode; input signals are inputted to the first terminal of a capacitor C, and its second terminal is kept at a reference potential to accumulate electrical charge in the capacitor C corresponding to the intensity of the input signals. In the second mode; the first terminal of the capacitor C is connected to the output terminal Tb
OUT of an operational amplifier 50b, and its second terminal is connected to the reverse input terminal Tb(-) of the operational amplifier 50b. The capacitor C contained in the memory unit 52 is composed of a well located on the surface of a semiconductor substrate, an insulating film formed on the well, and an electrode layer. The electrode layer serves as the first terminal of the capacitor C, and the well serves as the second terminal of the capacitor C.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：抑制开关电容电路中寄生电容的影响。解决方案：电路配备有至少一个包含开关元件Toa，Tia，Tob和Tib的存储单元52，并且能够选择第一模式或第二模式。在第一种模式下输入信号被输入到电容器C的第一端子，并且其第二端子保持在基准电位，以对应于输入信号的强度累积电容器C中的电荷。在第二种模式下电容器C的第一端子连接到运算放大器50b的输出端子Tb OUT ，其第二端子连接到运算放大器50b的反向输入端子Tb（ - ）。包含在存储单元52中的电容器C由位于半导体衬底的表面上的阱，形成在阱上的绝缘膜和电极层组成。电极层用作电容器C的第一端子，阱用作电容器C的第二端子。（C）2007，JPO＆INPIT

40. 发明专利

JP2007036873A Video signal processing apparatus 审中-公开
标题翻译：视频信号处理设备
公开(公告)号：JP2007036873A
公开(公告)日：2007-02-08
申请号：JP2005219376
申请日：2005-07-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： MEYA MASATO
IPC分类号： H04N5/14
摘要： PROBLEM TO BE SOLVED: To provide a signal processing circuit suitable for processing high-frequency signals. SOLUTION: By constituting a video signal processing apparatus by appropriately combining an adding circuit, including a switched capacitor circuit, a subtracting circuit, and an analog memory circuit, a high-frequency video signal can be properly processed. COPYRIGHT: (C)2007,JPO&INPIT

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