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31. 发明专利

JP2002132746A DATA PROCESSOR AND SINGLE CHIP MICROCOMPUTER 审中-公开
公开(公告)号：JP2002132746A
公开(公告)日：2002-05-10
申请号：JP2001246994
申请日：2001-08-16
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G06F12/14 , G06F9/46 , G06F9/48 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To improve safety in a system in the on-board write of a program memory. SOLUTION: While performing erasing processing or writing processing of an electrically erasable and writable program memory (18), an interruption request or exception processing request to a central processing unit(CPU) (12) is excluded or invalidated. Thus, while erasing or writing processing of the program memory (18) is performed, the CPU (12) does not perform operation for acquiring a vector address corresponding to the interruption request or exception processing request. Therefore, a situation that the microcomputer runs away because of the illegal fetch of the vector address can be prevented, and safety in the system in the on-board write of the incorporated ROM (18) can be improved.

32. 发明专利

JP2000099346A DATA PROCESSOR 失效
公开(公告)号：JP2000099346A
公开(公告)日：2000-04-07
申请号：JP23951399
申请日：1999-08-26
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G06F15/78 , G06F9/06 , G06F9/46 , G06F9/48 , G06F11/00
摘要： PROBLEM TO BE SOLVED: To improve the system safety in an onboard write mode of a program memory. SOLUTION: A built-in RAM 13 is partly moved to a vector address area by a bus controller 27 so as to obtain a correct vector address even if an interrupt occurs while a built-in ROM 18 is kept in its erase or write mode. Thus, the runaway of a microcomputer is prevented and the system safety is improved in an onboard write mode of the ROM 18.

33. 发明专利

JPH01134616A INTEGRATED CIRCUIT WITH OSCILLATING CIRCUIT 失效
公开(公告)号：JPH01134616A
公开(公告)日：1989-05-26
申请号：JP29379687
申请日：1987-11-20
申请人： HITACHI LTD
发明人： ITO TAKASHI , ISHIBASHI KENICHI , FUNATSU KENZO , YASHIKI NAOKI , IWATA KATSUMI
IPC分类号： G06F1/04 , G06F1/06 , G06F1/08 , G06F1/32
摘要： PURPOSE:To mutually shift between a standard action mode and a low energy consumption mode without generating a malfunction at a system by providing a stop mode and switching an internal block. CONSTITUTION:A system clock signal phiOSC from an oscillating circuit OSC1 and a clock signal phiCL for timing from an OSC2 are given to a multiplexer MPX, one side is selected in accordance with the setting condition of a flag FLG1 for designating a clock and sent to a pulse generating circuit CPG. The CPG forms several types of internal clocks having a different phase from an input clock. When '1' is set to a flag FLG2 by a stop instruction, the supply of the clock to the CPG is turned off. Next, when the flag FLG1 is set by the output of a timer interrupting circuit TIC, the timing function is executed by a low energy consumption mode based on the phiCL with a system. At the time of stopping mode, the FLG1 is cleared by the output of an external interrupting control circuit EIC, and then, an action is operated with a high clock from the CPG.

34. 发明专利

JPS6381536A ONE-CHIP MICROCOMPUTER 失效
公开(公告)号：JPS6381536A
公开(公告)日：1988-04-12
申请号：JP22599086
申请日：1986-09-26
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G06F9/46 , G06F9/48 , G06F15/78
摘要： PURPOSE:To attain high speed task switching while contriving high density by accessing a RAM so as to apply write for the read of a program counter and its stepping operation, accessing a built-in ROM according to an address of the program counter so as to read an instruction word. CONSTITUTION:A memory-ware to which bits constituting the program counter and various registers are assigned is provided to plural memory cells whose address is designated in a built-in RAM. Then the RAM is accessed to apply read of the program counter and the write for the stepping in a 1st stage and the built-in ROM is accessed according to the address of the program counter in a 2nd stage to read an instruction, and a prescribed information processing is applied based on the step of processing. Thus, the program counter and various registers are arranged in the RAM, then high circuit integration is contrived.

35. 发明专利

JPS59210587A Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：JPS59210587A
公开(公告)日：1984-11-29
申请号：JP8274483
申请日：1983-05-13
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： KII YOSHIO , IWATA KATSUMI , FUNATSU KENZOU , HOTSUTA SHINKICHI
IPC分类号： G11C11/417 , G11C11/34
CPC分类号： G11C11/34
摘要： PURPOSE:To reduce current consumption of a built-in RAM and reduce current consumption of the whole LSI in an LSI provided with an RAM by forming the precharge signal of a data line basing on an access signal. CONSTITUTION:MOSFETs Q11-Q14 for precharging are provided in data lines D, D'. Precharge signal phiP is formed basing on an RAM access signal AC outputted from an RAM I/O and a system clock CK, and precharge MOSFETs Q11-Q14 on the data line are turned on by a Y decoder 3. Consequently, the data line in the RAM is precharged only at the time of accessing, and at the same time, precharging is performed only for selected data line. Thus, current consumption is reduced remarkably.
摘要翻译：目的：通过基于访问信号形成数据线的预充电信号，减少内置RAM的电流消耗，并降低设置在RAM的LSI中的整体LSI的电流消耗。构成：在数据线D，D'中提供用于预充电的MOSFET Q11-Q14。预充电信号phiP基于从RAM I / O和系统时钟CK输出的RAM访问信号AC形成，数据线上的预充电MOSFET Q11-Q14由Y解码器3导通。因此，数据线 RAM仅在访问时被预充电，并且同时仅对选择的数据线执行预充电。因此，电流消耗显着降低。

36. 发明专利

JPS59134867A Resistance ladder 失效
标题翻译：电阻梯
公开(公告)号：JPS59134867A
公开(公告)日：1984-08-02
申请号：JP722283
申请日：1983-01-21
申请人： Hitachi Ltd
发明人： IWATA KATSUMI , KUBOKI SHIGEO , BABA SHIROU
IPC分类号： H03M1/76 , H01L21/822 , H01L27/04 , H01L27/08
CPC分类号： H01L27/0802
摘要： PURPOSE:To obtain a resistance ladder of small area by extending an FET in a diretion to face each other from the ladder row when longitudinally connecting in series a plurality of resistors, connecting switching MOSFETs with the respective resistors to form the ladder, and commonly using a well region and a contacting hole. CONSTITUTION:Resistor rows of a high voltage side Vref line 1 and a low voltage side AVSS line 2 are extended in parallel in proximity, and the ends are connected to the next resistor row via aluminum wirings is ?-shape. 16 resistors R1-R16 summed from 4 resistors per each row of four rows are connected in series of line rows of the lines 1, 2, switching MOSFET elements M1-M16 which corespond to the resistors are connected to both sides of the lines as a resistance ladder. In this structure, the opposing elements M1 and M9, M6 and M10, M7 and M11, M8 and M12 disposed inside the ?-shape therein are commonly used in a well region W provided inside the ?-shaped side, and the contacting holes further provided here are commonly used.
摘要翻译：目的：通过将纵向串联连接多个电阻器的方式将FET扩展到梯形排，以获得小面积的电阻梯，将开关MOSFET与相应的电阻器连接以形成梯形，并且通常使用井区和接触孔。构成：高压侧Vref线1和低电压侧AVSS线2的电阻行并联延伸，并且端部通过铝布线连接到下一个电阻器行。来自4排电阻器的4个电阻器中的16个电阻器R1-R16连接在线路1,2的串联行中，与电阻器对应的开关MOSFET元件M1-M16连接到线路的两侧作为电阻梯。在这种结构中，设置在其内的α形内部的相对元件M1和M9，M6和M10，M7和M11，M8和M12通常用于设置在α形侧内部的阱区W中，并且接触孔进一步这里提供的都是常用的。

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