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31. 发明专利

JPH01166633A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH01166633A
公开(公告)日：1989-06-30
申请号：JP32400087
申请日：1987-12-23
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TORII YUTAKA , KOMATSU AYAFUMI , YAMAMOTO MASAMI , MURAKAMI KENJIRO , HIRAIDE KAZUHIRO
IPC分类号： H04L7/00 , H04J3/06
摘要： PURPOSE:To establish the synchronization even if any phase difference exists between an external clock and an internal clock by providing a FF set by an AND signal between a clock whose pulse width is twice that of the external clock and the internal clock. CONSTITUTION:The FF 25 is set/reset by an AND signal between clocks 31, 32 formed by the external clocks 31, 32 and the internal clock. In such a case, the trailing edge of an output signal 35 of the FF 25 is delayed a little from the leading edge of the internal clock due to a delay in the FF 25 or the like. Since the leading edge of the internal clock exists in the pulse width (T) time of the output signal 35 without fail, an output signal 36 of a FF 26 rises synchronously with the leading edge of the internal clock and the pulse width reaches T. The output 33 of the FF 21 is selected by the signal 36, the selected signal 37 is segmented by the trailing edge of the internal clock to obtain an output data.

32. 发明专利

JPS6436142A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPS6436142A
公开(公告)日：1989-02-07
申请号：JP19007787
申请日：1987-07-31
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOMATSU AYAFUMI , TORII YUTAKA , MURAKAMI KENJIRO
IPC分类号： H04J3/06 , H04L7/00 , H04L7/033
摘要： PURPOSE:To attain synchronization in a short time while obtaining larger margin against the fluctuation of an input signal by extracting a delay signal synchronously with the rise of a clock by using a clock delayed by a prescribed time more than the former clock. CONSTITUTION:A delay section 10 retarding sequentially an input signal with a prescribed delay and extracting the delayed signal for each delayed value and n-set of latch sections 30 extracting simultaneously delay signals having n-kind of delay values outputted from the delay section 10 by using a set signal synchronously with a clock CK 1 respectively, are provided. Moreover, a detection section 40 comparing the state of the i-th and (i+1)th outputs from each latch section 30, and detecting the change point of the state, and an output section 50 fetching a delay signal whose change point is detected and picking up the delay signal by means of a clock CK 2 retarded from the clock CK 1 by a prescribed delay and obtaining an output signal, are provided. Thus, the output signal synchronously with the clock CK 1 is obtained, a short time is enough for setting the title circuit and the bit phase synchronizing circuit having a larger margin with respect to the fluctuation of the input signal is obtained.

33. 发明专利

JPS63169156A CIRCUIT FOR DETECTING LINE DISCONNECTION FAULT 失效
公开(公告)号：JPS63169156A
公开(公告)日：1988-07-13
申请号：JP38487
申请日：1987-01-07
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOMATSU AYAFUMI , HORIKI AKIRA , SANPEI TAKESHI , YAMADA HIROKI
IPC分类号： H04M3/22
摘要： PURPOSE:To detect a line disconnection by providing a flip flop which indicates the closing and the releasing of a switch while corresponding an outgoing line and an AND circuit which calculates the AND of the output of the flip flop and the output of a signal interruption detecting circuit. CONSTITUTION:When a fault occurs, a signal interruption detector 2 detects this fault, indicates the fault and at the same time an idle signal is outputted. For example, when binary information indicates zero-th line, the output OSO of a decoder goes to high level, a gate 7 transmits a set signal to the flip flop FF zero and the flip flop FF zero outputs a high level signal to the AND circuit. When the fault occurs at the zero-th line and the circuit is in the state of no signal, a signal interruption detecting circuit 2 outputs the high level signal and the output of the AND circuit turns to the high level. Then the fault corresponding with the line is displayed. Thus the disconnection of the line can be detected in the course of transmitting the idle signal.

34. 发明专利

JPS62268245A CONTINUITY TEST SYSTEM 失效
公开(公告)号：JPS62268245A
公开(公告)日：1987-11-20
申请号：JP11081686
申请日：1986-05-16
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOMATSU AYAFUMI , SANBE TAKESHI
IPC分类号： H04M3/26
摘要： PURPOSE:To eliminate the need for a terminal and the hardware exclusively for the test by providing a loop back setting to the interface section of photoelectric/electrooptic signal conversion and using an idle signal informing the open channel to an opposite transmission equipment so as to conduct the continuity test for the channel. CONSTITUTION:In testing a path 1 between a B.I terminal and an A.O terminal between interface sections SDCA and SDCB of photo electric/electrooptic conversion corresponding to input/output lines, a specific pattern signal from an IDLE is returned to the DET of the IDLE via the path of IDLE (signal device)-T.I terminal-SSW(channel)-B.O terminal-TST loopback of SDCB-B.I terminal-path 1-A.O terminal-TST loopback of SDCA-A.I terminal-SSW T.O terminal-DET (detector) of IDLE so as to discriminate whether or not a normal path is formed. If the path is not normally completed, the path 2 is checked by the DET of the SDCB, the path 1 is checked by the DET of the SDC A and the path 3 is checked by the DET of the IDLE to decide which path is faulty.

35. 发明专利

JPS6260347A SIGNAL PROCESSING SYSTEM IN SIGNAL COMMUNICATION 失效
公开(公告)号：JPS6260347A
公开(公告)日：1987-03-17
申请号：JP19946485
申请日：1985-09-11
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KOMATSU AYAFUMI , UENO SUSUMU
IPC分类号： H04M7/14
摘要： PURPOSE:To simplify a time division switch section by writing a signal on a memory in the order of incoming signal, applying time slot conversion and providing a circuit section extracting a specific time slot only. CONSTITUTION:A signal S0 is written sequentially on addresses designated by a counter CNT in the incoming order to a memory M such as A0, D0, A1, D1...A31, D31. Then the address is written in the above order on a ROM so as to be read in the order of A0-A31 and D0-D31 and the output of the memory M is A0-A31, D0-D31 by accessing the address of the memory M via a selector SEL. Data CS0 is fetched in a flip-flop DF by controlling a clock CLK 2 to be outputted at the timing of CS0 in the signal S0. The CS signal in each TSR is used as an input to a multiplexer MPX and controlled to obtain an output in the order of CS0-CS15 by using a clock CLK 3.

36. 发明专利

JPH0236631A BIT PHASE SYNCHRONIZING CIRCUIT 失效
公开(公告)号：JPH0236631A
公开(公告)日：1990-02-06
申请号：JP18563688
申请日：1988-07-27
申请人： HITACHI LTD , HITACHI COMMUNICATION SYSTEM
发明人： NISHI YUMIKO , KOMATSU AYAFUMI , TORII YUTAKA , TAKAGI SEIICHI
IPC分类号： H04L7/00
摘要： PURPOSE:To reduce the effect of dispersion in a gate delay time by ORing with a double clock and inverse of the double clock and using a clock so as to extract the signal being the result of ORing of the said outputs. CONSTITUTION:A clock inverse of 2ck and a data D1 are supplied to two input terminals of an AND gate 41 in an output gate extraction section 40 and a clock 2ck and a data D2 are given to two input terminals of an AND gate 42. Since the clocks 2ck, inverse of 2ck reach an H level alternately, the data D1, D2 are given to an OR gate 52 of an output section 50. Output signals DA, DB of the AND gates 41, 42 are signals being the result of synchronizing the H level of the input signal DI with the clock 2ck. Then the signals DA, DB inputted to the output section 50 are ORed by an OR gate 52, the result is a signal DD synchronously with the clock ck, the signal DD is extracted just in the center by using the clock, inverse of ck by a flip-flop 51 and the result becomes an output data DO. Thus, the effect due to the dispersion in the gates is avoided.

37. 发明专利

JPS61290847A BIT ERROR DETECTING SYSTEM 失效
公开(公告)号：JPS61290847A
公开(公告)日：1986-12-20
申请号：JP13178685
申请日：1985-06-19
申请人： HITACHI LTD
发明人： KOMATSU AYAFUMI
IPC分类号： H04L25/02 , G06F11/22 , H04M3/26 , H04Q1/24
摘要： PURPOSE:To detect easily a bit error by non-adjustment, by reading a test pattern which has been written in a memory in accordance with an indication of a detected frame signal, and making the test pattern which has been read out of the memory coincide with the test pattern which has passed through a channel to be measured. CONSTITUTION:A data of a test pattern (A) is written to an address '0' from a head data in a memory M, a read-out address '0' of the memory M is designated by a frame signal for showing a head data of a test pattern (B) which has passed through a switch to be tested SW, the data of the test pattern (A) is read out of the head, and the data of the test pattern (B) coincided with the phase. When the test pattern (A), and the test pattern (B) are inputted to one input of this EXOR and the other input, respectively, as for a logic of the EXOR, when the input data coincides, this output becomes '0', and in case of dissidence, it becomes '1'. Accordingly, a bit error can be detected in accordance with whether the output of the EXOR becomes '1' or not.

38. 发明专利

JPS5958994A Information transmission system of exchange system 失效
标题翻译：交换系统信息传输系统
公开(公告)号：JPS5958994A
公开(公告)日：1984-04-04
申请号：JP16830982
申请日：1982-09-29
申请人： Hitachi Ltd
发明人： KANO HARUKIYO , KOMATSU AYAFUMI
IPC分类号： H04Q3/545 , G06F9/445 , G06F13/00 , H04Q11/04
CPC分类号： H04Q11/0407
摘要： PURPOSE:To attain economically the reduction in a loading time of a program, by transferring a program stored in one module to other module via an exchange switch. CONSTITUTION:Modules 1-0-1-32 are linked with a control bus 5, a pair of modules (e.g., 1-0 and 1-32) transmit/receive information mutually at the same time, and the information generated from a specified module (e.g., 1-32) is received by other entire modules (e.g., 1-0-1-31). Further, the modules 1-0-1-32 and a time division switch 4 are connected with communication buses 3-0-3-32 and an optional time slot between an optional communication bus and the other optional communication bus 3 is exchanged and connected by controlling the time division switch 4 with the modules 1-0-1-32 via the control bus 5.
摘要翻译：目的：通过经由交换机将存储在一个模块中的程序传送到其他模块，实现经济上减少程序加载时间。规定：模块1-0-1-32与控制总线5，一对模块（例如，1-0和1-32）同时相互发送/接收信息以及从指定的信号生成的信息模块（例如，1-32）由其他整个模块（例如，1-0-1-31）接收。此外，模块1-0-1-32和时分开关4与通信总线3-0-3-32连接，并且可选通信总线与另一可选通信总线3之间的可选时隙被交换和连接通过控制总线5通过模块1-0-1-32控制时分开关4。

39. 发明专利

JPS5883457A COMMON USE METHOD FOR FILE MEMORY 失效
公开(公告)号：JPS5883457A
公开(公告)日：1983-05-19
申请号：JP18110481
申请日：1981-11-13
申请人： HITACHI LTD
发明人： KOMATSU AYAFUMI , KANO HARUKIYO
IPC分类号： H04M3/00
摘要： PURPOSE:To efficiently use a file memory in common, by performing the write/ readout/transfer among exchanges to a file memory in common use for each exchange in the common format, through the correspondence of data at various terminals to one common format. CONSTITUTION:In dialing a selected code at a terminal 1, a network controller in a common control section 10 connects the terminal 1 and an FAX trunk 6 via a bus 20. Then, this data is fetched to a file memory 17 to store and exchange the data at the terminal 1. This is performed by connecting the trunk 6 and a data controller 11 via a bus 21 through a file memory controller 16. The data are converted into a common format at the controller 16. Thus, the data storage file memory at various terminals can be used in common, allowing to simplify and economize the system.

40. 发明专利

JPS574690A TIME-DIVISION EXCHANGE SYSTEM 失效
公开(公告)号：JPS574690A
公开(公告)日：1982-01-11
申请号：JP7775080
申请日：1980-06-11
申请人： HITACHI LTD
发明人： KOMATSU AYAFUMI
IPC分类号： H04Q11/04
摘要： PURPOSE:To increase the capacity of a switchboard with an addition of a slight amount of facilities, by exchanging the call data with an alternating use of n sets of time-division exchange parts. CONSTITUTION:In the case of highway HWA, a reading is possible unless the front side T switch FTSWA is in a writing mode. Then a writing becomes possible if the rear side T switch RTSWA is not in a reading mode. AN exchange on the highway HWA is carried out when the switch FTSWA and the switch RTSWA are in a reading mode and a writing mode respectively. Thus the number of exchangeable channels is three times as much as the conventional number.

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