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31. 发明专利

JPH0615434B2 失效
公开(公告)号：JPH0615434B2
公开(公告)日：1994-03-02
申请号：JP17485585
申请日：1985-08-08
申请人： HITACHI LTD
发明人： KURIHARA YASUTOSHI , INOE KOICHI , TAKAHASHI MASAAKI , SAWAHATA MAMORU , YATSUNO KOMEI
IPC分类号： C04B41/88

32. 发明专利

JPH0586855B2 失效
公开(公告)号：JPH0586855B2
公开(公告)日：1993-12-14
申请号：JP6367385
申请日：1985-03-29
申请人： HITACHI LTD
发明人： MURAKAMI SUSUMU , KAGAMI TERUYUKI , TAKAHASHI MASAAKI , KARYA TADAAKI
IPC分类号： H01L23/52 , H01L21/312 , H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/822 , H01L27/04

33. 发明专利

JPH04211191A SUBSTRATE WITH BUILT-IN CAPACITOR 失效
公开(公告)号：JPH04211191A
公开(公告)日：1992-08-03
申请号：JP1745191
申请日：1991-02-08
申请人： HITACHI LTD
发明人： SHINOHARA KOICHI , INOUE KOICHI , ABE YOICHI , KATO AKIRA , SUZUKI HIDEO , YAMADA KAZUJI , TAKAHASHI MASAAKI , NAKANISHI KEIICHIRO
IPC分类号： H01B3/00 , H01G4/12 , H01L25/00 , H01L25/04 , H01L25/18 , H05K1/16
摘要： PURPOSE:To reduce the occurrence of high-frequency switching noise which is generated when logic circuits are simultaneously switched by reducing the inductance between an LSI and a capacitor formed on a substrate. CONSTITUTION:A capacitor is formed so that the inductance between the bonding pad of an LSI mounted on a ceramic substrate 3 and the electrode 7 of the capacitor can be suppressed to 0.05nH. Since the inductance between the LSI and the capacitor is suppressed, the high-frequency component of the noise generated by power supply can be reduced. Therefore, the rise time of signals can be shortened and the operating can be increased.

34. 发明专利

JPH01184854A MOUNTING STRUCTURE OF HIGH THERMAL CONDUCTIVITY SEMICONDUCTOR 失效
公开(公告)号：JPH01184854A
公开(公告)日：1989-07-24
申请号：JP476188
申请日：1988-01-14
申请人： HITACHI LTD
发明人： INOUE KOICHI , KURIHARA YASUTOSHI , OKADA NOBUSUKE , TANAKA AKIRA , TAKAHASHI MASAAKI
IPC分类号： H01L23/40 , H01L23/36
摘要： PURPOSE:To keep the thermal resistance of a semiconductor device small, by keeping always the thickness of a resin layer of the lower side of a semiconductor chip sufficiently small, and making the thickness of the resin layer except the lower side of the semiconductor chip comparatively large. CONSTITUTION:Silicon semiconductor chips 1 are arranged in a line on a dielectric substrate 6 of high thermal conductivity, via eutectic solder 5. Protrusions 10 are formed on the surface of the substrate 6 under the semiconductor chips 1 where the semiconductor chips 1 are not attached. The substrate 6 is bonded to a package case 2 constituted of aluminum alloy, via silicon system organic adhesive agent 7. Although air bubbles 15 exist in the organic adhesive agent 7, they are trapped in a part of the thick adhesion layer whose thickness is kept 100mum or more, and do not exist in the thin adhesion layer whose thickness is kept 30mum or less by the protrusions 10. As a result, the thermal resistance of a semiconductor device can be remarkably improved.

35. 发明专利

JPH0117261B2 失效
公开(公告)号：JPH0117261B2
公开(公告)日：1989-03-29
申请号：JP9071883
申请日：1983-05-25
申请人： HITACHI LTD
发明人： MISAWA YUTAKA , HIDAKA TOSHUKI , SAKAMOTO HISASHI , TAKAHASHI MASAAKI , YATSUNO KOMEI
IPC分类号： C08G59/40 , C08G59/50 , H01L23/29 , H01L23/31

36. 发明专利

JPS6257239A ALUMINUM NITRIDE SUBSTRATE FOR MOUNTING SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS6257239A
公开(公告)日：1987-03-12
申请号：JP19590485
申请日：1985-09-06
申请人： HITACHI LTD
发明人： TAKAHASHI MASAAKI , KURIHARA YASUTOSHI , INOUE KOICHI , SAWAHATA MAMORU , YATSUNO KOMEI
IPC分类号： H01L23/15 , H05K1/02 , H05K1/03 , H05K3/22
摘要： PURPOSE:To improve corrosion behavior of an aluminum nitride substrate with respect to water and to make electric characteristics excellent, by forming a protecting layer on the surface of the substrate other than a metallized-layer forming part, with regard to the metarial of a ceramic substrate for mounting semiconductor integrated circuit such as an LSI and a VLSI. CONSTITUTION:A metallized layer is formed on the surface of a substrate constituting a sintered body, whose main component is aluminum nitride. In this device, a metallizing paste is applied on the surface of the aluminum nitride substrate. Then temperature is increased in a weak oxidizng atmosphere. On the surface of the substrate other than the paste forming part, an aluminum oxide layer and/or a boehmite layer is formed. Then, the device is burned in an reducing atmosphere of the paste. Thereafter, the temperature is decreased in the same atmosphere. It is desirable that a material, which is decomposed in heating in the weak oxidizing atmosphere and discharges oxygen, is included in the paste. It is desirable that the aluminum oxide and/or the boehmite layer has the thickness of less than 2mum, i.g., 0.1-1mum.

37. 发明专利

JPS6217091A METALLIZATION FOR ALUMINUM NITRIDE BODY 失效
公开(公告)号：JPS6217091A
公开(公告)日：1987-01-26
申请号：JP15590285
申请日：1985-07-17
申请人： HITACHI LTD
发明人： KURIHARA YASUTOSHI , INOUE KOICHI , TAKAHASHI MASAAKI , SAWATOMI MAMORU , YATSUNO KOMEI
IPC分类号： C04B41/88

38. 发明专利

JPS61224343A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61224343A
公开(公告)日：1986-10-06
申请号：JP6367385
申请日：1985-03-29
申请人： HITACHI LTD
发明人： MURAKAMI SUSUMU , KAGAMI TERUYUKI , TAKAHASHI MASAAKI , KARIYA TADAAKI
IPC分类号： H01L23/52 , H01L21/312 , H01L21/3205 , H01L21/76 , H01L21/762 , H01L21/822 , H01L27/04
摘要： PURPOSE:To obtain a highly reliable IC device by a method wherein a resistance film is formed on the final insulating film formed on the mutually isolated single crystal Si islands and the Si islands are connected with the polycrystalline Si substrate at the connecting parts. CONSTITUTION:Numerous n-type single crystal islands 3, which are mutually isolated by SiO2 films 2, are formed in a polycrystalline Si substrate 1. N layers 4, a p-type emitter 5, an n emitter 6, a p-type base 7, a p-type resistance layer 8, an anode electrode 9 to be coupled with the p-type emitter 5, a cathode electrode 10 to be coupled with the n emitter 6, a gate electrode 11 to be coupled with the p-type base 7, electrodes 12 and 13 to be coupled with the p-type resistance layer 8 and insulating film 14 and 15 are respectively formed as prescribed, the insulating film 15 is covered with a polycrystalline Si resistance film 16 and the single crytal islands are connected with the polycrystalline Si substrate 1 at connecting parts 17. In this constitution, when the substrate 1 is earthed, each island 3 is surrounded with the earth potential in a three-dimensional manner and is shielded from the external atmosphere, and moreover, the intrusion of water content and Na ions into the islands from the extermal atmosphere is also prevented. As a result, the highly reliable device can be obtained.

39. 发明专利

JPS61114574A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS61114574A
公开(公告)日：1986-06-02
申请号：JP23498984
申请日：1984-11-09
申请人： Hitachi Ltd
发明人： MURAKAMI SUSUMU , KAGAMI TERUYUKI , YAO TSUTOMU , TAKAHASHI MASAAKI
IPC分类号： H01L29/73 , H01L21/314 , H01L21/331 , H01L29/06 , H01L29/40 , H01L29/732 , H01L29/74
CPC分类号： H01L29/405 , Y10S257/905
摘要： PURPOSE: To improve the resistance to voltage and the reliability, by providing a resistive material sheet electrically connected with a semiconductor layer having a potential substantially equal to that of the main electrode, on a surface-stabilizing insulation film provided on the exposed surface of a semiconductor substrate.
CONSTITUTION: A semiconductor substrate 100 is provided, between its upper and lower surfaces, with an n
+ type emitter layer 1, a p type base layer 2 having a higher concentration of impurity in the surface region and having the lower concentration in proportion to the depth, a high-resistance n type collector layer 3, an n
+ type channel-cut layer 5, emitter, collector, base and channel-cut electrodes 6, 7, 8 and 9, an insulation film 10, an amorphous silicon film 11 and the like. The film 11 is connected with the layers 1 and 3 through the electrodes 6 and 9. Accordingly, a depletion layer is provided over the surface of the layer 3, whereby the resistance to voltage of the device can be improved. Further, since the film 11 is directly connected with the electrodes 7 and 9, the decrease in resistance to voltage between the emitter and the collector, which would be caused by the transistor effect induced by leak current flowing through the film 11, can be effectively prevented.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了提高耐电压性和可靠性，通过提供与具有与主电极的电位基本相同的电位的半导体层电连接的电阻材料片，在设置在电极的暴露表面上的表面稳定绝缘膜上半导体衬底。构成：半导体衬底100在其上表面和下表面之间设置有n +型发射极层1，在表面区域具有较高浓度的杂质的具有较低浓度的p型基极层2，深度，高电阻n型集电极层3，n +型沟道切割层5，发射极，集电极，基极和沟道切割电极6,7,8和9，绝缘膜10，非晶体硅膜11等。膜11通过电极6和9与层1和3连接。因此，在层3的表面上提供耗尽层，从而可以提高器件的耐电压。此外，由于膜11与电极7,9直接连接，所以由流过膜11的漏电流引起的晶体管效应引起的发射极与集电极之间的电压的降低可以有效地防止了

40. 发明专利

JPS59186344A Manufacture of semiconductor device 失效
标题翻译：半导体器件的制造
公开(公告)号：JPS59186344A
公开(公告)日：1984-10-23
申请号：JP5927683
申请日：1983-04-06
申请人： Hitachi Ltd
发明人： MISAWA YUTAKA , TAKAHASHI MASAAKI , YATSUNO KOUMEI , HIDAKA TOSHIYUKI , SAKAMOTO HISASHI
IPC分类号： H01L21/301 , H01L21/302 , H01L21/3065 , H01L21/78
CPC分类号： H01L21/78
摘要： PURPOSE:To prevent generation of deterioration of characteristic and irregular characteristic by previously cutting the wafer so that the semiconductor wafer plane coincides with both orientations of pellet side planes on the occasion of executing the alkali etching or plasma etching using any of CCl4-O2, CF3Br, CCl4 to the semiconductor pellets being cut into the specified size. CONSTITUTION:A PIN structure semiconductor element is formed using an Si wafer having the plane orientation (100) of front and rear planes and the orientation flat OF (100). On the occasion of obtaining the pellets, cutting is performed in parallel to or at a right angle to the flat OF and also at a right angle to the front and rear planes. Thus, orientation of all planes of pellet 2 are set to (100) and the copper leads 5, 6 are clamped to the front and rear planes using solders 3, 4. When, pellets are obtained in such structure, alkali or plasma etching should be performed previously to the pellet 2.
摘要翻译：目的：为了通过预先切割晶片以防止在执行使用CCl4-O2，CF3Br中的任一种的碱蚀刻或等离子体蚀刻的情况下半导体晶片平面与颗粒侧面的两个取向一致的特性和不规则特性的劣化，，将CCl4切割成规定尺寸的半导体颗粒。构成：使用具有前平面和后平面的平面取向（100）和取向平面OF（100）的Si晶片形成PIN结构半导体元件。在获得颗粒的情况下，与平面OF平行或直角进行切割，并且与前后平面成直角。因此，将颗粒2的所有平面的取向设定为（100），并且使用焊料3,4将铜引线5,6夹紧到前平面和后平面。当以这种结构获得颗粒时，应进行碱蚀刻或等离子体蚀刻以前要进行颗粒2。

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