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31. 发明专利

JPS63268376A VIDEO SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS63268376A
公开(公告)日：1988-11-07
申请号：JP10191387
申请日：1987-04-27
申请人： HITACHI LTD
发明人： OKUDA AKIHIDE , NAKAGAWA HIMIO , HIRANO YASUHIRO
IPC分类号： H04N5/208
摘要： PURPOSE:To improve the picture quality of animation mode as keeping high resolution in the picture quality of a still picture mode, by providing a high range emphasizing circuit for the animation mode and that for the still picture mode, and performing the weight adding calculation on the outputs of the above two circuits corresponding to their motion quantities. CONSTITUTION:A YCYH separation circuit 4 separates and outputs a Y signal, a C signal, and an HH signal by switching an inter-frame arithmetic operation, an inter-field arithmetic operation, an interline arithmetic operation, and frequency separation, etc., based on the motion quantity. A motion detection circuit 9 detects the motion quantities by taking the inter-two frame difference and the inter-frame difference, etc., of a Y and inputs them to a scanning line interpolation circuit 10 and a weight addition circuit 13. The scanning line interpolation circuit 10 interpolates a scanning line by switching inter-frame interpolation and inter-line interpolation. A wide band area high range emphasizing circuit 11 and a narrow band area high range emphasizing circuit 12 emphasizing the Y respectively. The weight adder circuit 13 performs addition by multiplying the outputs of the wide band area high range emphasizing circuit 11 and the narrow band area high range emphasizing circuit 12 by weight corresponding to the motion quantity.

32. 发明专利

JPS63193783A N-FOLD SCAN TELEVISION RECEIVER 失效
公开(公告)号：JPS63193783A
公开(公告)日：1988-08-11
申请号：JP2458587
申请日：1987-02-06
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： SEKIYA HIROSHI , MURATA TOSHINORI , KURITA TOSHIYUKI , ARAI IKUYA , NAKAGAWA HIMIO
IPC分类号： H04N7/01 , G09G1/04 , G09G1/16 , G09G5/12
摘要： PURPOSE:To improve a phase error answer when a normal horizontal synchronizing signal is inputted by constituting a two-fold horizontal synchronism generation circuit and a two-fold horizontal deflection circuit in one phase locked loop circuit. CONSTITUTION:A phase locked loop circuit 9 consists of a phase comparator 13, a low pass filter 14, a voltage controlled oscillator 15 and a 1/2 frequency divider 19. A 1/910 frequency divider 18 is provided before the phase synchronous circuit 9, and it always operates the phase comparator 13 with a normal horizontal synchronizing frequency. If the normal horizontal synchronizing signal is selected as an input signal, the normal horizontal synchronizing signal is inputted to the phase comparator 13. If an n-fold horizontal synchronizing signal is selected, the horizontal synchronizing signal whose frequency has become the same as the normal horizontal synchronizing signal by the 1/910-frequency divider is inputted to the phase comparator 13. For switching a standard signal and the two-fold signal as the input signal, the phase synchronous circuit of horizontal synchronism can be constituted in one stage, whereby the same phase error answer can be obtained. If the normal signal is inputted, the phase error answer can considerably be improved.

33. 发明专利

JPS63187818A CLOCK SYNCHRONIZATION TYPE COUNTER CIRCUIT 失效
公开(公告)号：JPS63187818A
公开(公告)日：1988-08-03
申请号：JP1836287
申请日：1987-01-30
申请人： HITACHI LTD
发明人： SASAKI EIKO , TSUKASAKI HISANOBU , MATSUMOTO SHUZO , KONDO KAZUO , NAKAGAWA HIMIO , KOJIMA NOBORU , HORIUCHI SUNAO , ISHIKAWA SHINJI
IPC分类号： H03K23/40 , H03K23/00 , H03K23/50
摘要： PURPOSE:To reduce the circuit area and to attain high speed operation by providing two kinds of counter circuits, 1st and 2nd counter circuits, and connecting directly the high-order digits and the low-order digits. CONSTITUTION:An input signal from a terminal 1 and an output signal of an inverter 12 are inputted to an OR gate 4 and a NAND gate 5 of a counter circuit 17, and the NAND gate 5 outputs a carry signal to a high-order digit counter circuit 18. A carry signal from the counter circuit 17 and an output signal of the inverter 13 are inputted to a NOR gate 7 and an AND gate 8 of the counter circuit 18 and the carry signal is outputted from the NOR gate 7 to the high-order digit of the counter circuit 19. Moreover, the counter circuit 19 outputs a carry signal to the counter circuit 20 similar to the counter circuit 17 and the counter circuit 20 outputs the carry signal to the output terminal 21 in the similar operation as the circuit 18. Thus, number of circuit components of the inverter circuit is reduced and the operating speed by the reduction in the number of components is quickened.

34. 发明专利

JPS63126386A NON-STANDARD SIGNAL DETECTING CIRCUIT 失效
公开(公告)号：JPS63126386A
公开(公告)日：1988-05-30
申请号：JP27181086
申请日：1986-11-17
申请人： HITACHI LTD
发明人： ARAI IKUYA , MURATA TOSHINORI , KURITA TOSHIYUKI , SAKAMOTO TOSHIYUKI , NAKAGAWA HIMIO , ACHIHA MASAHIKO
IPC分类号： H04N9/44 , H04N9/87
摘要： PURPOSE:To simply and correctly detect a non-standard signal by comparing phase error signals between a vertical blanking period and a video period in a television receiver. CONSTITUTION:The oscillating output signal of a VCXO105 is compared in phase with a burst signal inputted from an input terminal 102 in a phase comparison circuit 103 for every burst period and a phase detection signal is outputted. Only the direct current component of this phase detection signal is taken out, the signal is converted to the phase error signal to be the control signal of the VCX 105. When the special reproduced signal of a VDP or the like is inputted, the phase of the burst signal is discontinuous in the vertical blanking period, thereafter, the oscillating frequency of the VCX 105 is changed according to the phase error signal, operated synchronously with the burst signal again after 10-20 horizontal scanning period, so that an APC circuit is stabilized during the video period.

35. 发明专利

JPS6390968A TELEVISION SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS6390968A
公开(公告)日：1988-04-21
申请号：JP23613986
申请日：1986-10-06
申请人： HITACHI LTD , HITACHI VIDEO ENG
发明人： NAKAGAWA HIMIO , SUZUKI SUNAO , HIRAHATA SHIGERU , SUGIYAMA MASAHITO , KATSUMATA KENJI
IPC分类号： H04N5/21 , H04N9/77
摘要： PURPOSE:To execute an optimum noise reduction with respect to a luminance signal and a color difference signal respectively, by setting the gain of a second noise reducing circuit whose gain is varied in accordance with magnitude of a difference of an input and an output of the second memory circuit to a larger value than that of the gain of a first noise reducing circuit whose gain is varied in accordance with magnitude of a difference between an input and an output of a first memory circuit. CONSTITUTION:The first noise reducing circuit 109 uses a difference of an input and an output of the first memory circuit 111 and decides whether its difference is caused by a noise or a motion of an image, and in case when it is decided to be a difference by a noise, the noise is reduced by controlling the gain of the difference and by a feedback to an input signal. When it is decided to be a difference by a motion of an image, zero is fed back and no noise reduction is executed. The second noise reducing circuit 110 is also constituted in the same way, but the gain of the second noise reducing circuit 110 is set to a larger value than the gain of the first noise reducing circuit 109, and when it is decided that a difference of an input and an output of the second memory circuit 112 is due to a noise, the noise reduction is executed by controlling the gain of the difference and by a feedback to an input signal. In this way, the gains of the first and the second noise reducing circuits 109, 110 can be controlled independently.

36. 发明专利

JPS6376591A TRANSMISSION SIGNAL GENERATING DEVICE 失效
公开(公告)号：JPS6376591A
公开(公告)日：1988-04-06
申请号：JP21936686
申请日：1986-09-19
申请人： HITACHI LTD
发明人： NAKAGAWA HIMIO , NODA TSUTOMU , KOBAYASHI MASAHARU , OKUDA AKIHIDE
IPC分类号： H04J11/00 , H04N7/08 , H04N7/081
摘要： PURPOSE:To contrive the multiplex transmission of a digital-coded signal having a high definition by modulating the orthogonal component of a carrier wave to be amplitude modulated with a video signal by using a digital-coded signal, thereby making the contents of the signal different between vertical fly-back period and other periods. CONSTITUTION:During a video signal period, the modulation is executed with a signal such as a sound signal digital-coded within a band to be transmitted in both side bands of the carrier wave, securing the orthogonal relation against the video signal in the carrier wave, and data of a high importance such as a synchronizing signal and a control signal are transmitted in periods other than a video signal period. In such a way, the carrier wave having both side bands is modulated with a video signal and the sound signal that are in the orthogonal relation within the limit of the band generally amplitude-modulated, accordingly, the influence of the sound signal on a reproduced video signal can be decreased. By making the degree of modulation of the sound signal lower than that of video signal, the influence of the sound signal on a video signal reproduced through envelope detection can also be reduced.

37. 发明专利

JPS6350183A PICTURE IMAGE SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS6350183A
公开(公告)日：1988-03-03
申请号：JP19270286
申请日：1986-08-20
申请人： HITACHI LTD
发明人： HORIUCHI SUNAO , KOJIMA NOBORU , HIRAHATA SHIGERU , NAKAGAWA HIMIO , TSUKASAKI HISANOBU , KONDO KAZUO , MATSUMOTO SHUZO , ISHIKAWA SHINJI , SASAKI EIKO
IPC分类号： H04N7/01
摘要： PURPOSE:To deal with the case where scanning interpolation other than line interpolation is made by initializing address value of a write address generating circuit at a period of horizontal synchronizing signals and initializing address value of a read address generating circuit at a period of double speed horizontal synchronizing signals from a double speed horizontal synchronizing signal cenerating circuit. CONSTITUTION:Video data of two systems, i.e. inputted real signals of sampling frequency f and interpolation signals, are led to a multiplexer 6, and each picture element is multiplexed to signals of double rate 2f, and written in a memory 1 according to write address generated by a write address generating circuit 2. The write address generating circuit 2 initializes the write address value to alpha0 at a period of horizontal synchronizing signals of frequency fH, and renews address values successively as alpha1, alpha2, alpha3... at every input of write clock of frequency 2f. A read address generating circuit 3 initializes read address values to alpha0 and alpha1 every time alternately at a period of double speed horizontal synchronizing signals of frequency 2f generated by a double speed horizontal synchronizing signal generating circuit 8.

38. 发明专利

JPS631281A SIGNAL PROCESSING CIRCUIT 失效
公开(公告)号：JPS631281A
公开(公告)日：1988-01-06
申请号：JP14302086
申请日：1986-06-20
申请人： HITACHI LTD
发明人： KURITA TOSHIYUKI , MURATA TOSHINORI , SAKAMOTO TOSHIYUKI , ARAI IKUYA , NAKAGAWA HIMIO , ACHIHA MASAHIKO , ISHIKURA KAZUO
IPC分类号： H04N9/78 , H04N7/01 , H04N11/20
摘要： PURPOSE:To prevent the malfunctions of movement detection and a YC separating circuit by providing a means which detects the non-reverse state of a color burst phase and a means which performs switching between adaptive signal processing in a time space and the signal processing in a space only to detect the phase non-reverse state of a color burst signal and setting the signal processing in the space only. CONSTITUTION:When a signal conforming to the standard of a NTSC signal is supplied, a color burst non-reverse state detecting circuit 106 detects that the phase of the color burst signal is inverted between frames. Then a switching circuit 110 is actuated so that the output of a movement-adaptive scan line interpolation circuit 105 is transmitted. While in case of a reproduction signal obtained in a special reproduction mode of a VTR or a VDP, the circuit 106 switches the circuit 110 so that the output of an intra-space scan line interpolation circuit 109 is transmitted. Then the video signals processed through an intra-space YC separating circuit 107, a RGB converting circuit 108 and the circuit 109 are sent to a time compressing/multiplexing circuit 111. As a result, signal processing is possible in a space area having the most intensive correlation. Thus the malfunctions of movement detection can be avoided.

39. 发明专利

JPS62291282A TELEVISION RECEIVER 失效
公开(公告)号：JPS62291282A
公开(公告)日：1987-12-18
申请号：JP13361986
申请日：1986-06-11
申请人： HITACHI LTD
发明人： ARAI IKUYA , MURATA TOSHINORI , NAKAGAWA HIMIO , SAKAMOTO TOSHIYUKI
IPC分类号： H04N9/00 , H04N9/78
摘要： PURPOSE:To attain the optimum filter processing for a non-reference signal, by discriminating whether prescribed relation between a chrominancc subcarrier frequency, and a frame frequency can be obtained, and selecting a filter circuit corresponding to the above discriminated result. CONSTITUTION:From a composite video signal inputted from an input terminal 100, a reference signal and the non-reference signal are detected and discriminated between a burst extraction circuit 107 and an integration circuit 114. Meanwhile, a motion detection signal is detected at a motion detection circuit 115, and the motion detection signal, an external control signal inputted from an external terminal 117, and the above discrimination signal are added on an AND circuit 116. And switches 103 and 104 are operated by the output of the AND circuit 116, and either output of a frame comb type filter 101, or a line comb type filter is selected. In this way, the output of the line comb type filter is selected at the time of detecting the non-reference signal, detecting the motion of an image, and inputting the external control signal.

40. 发明专利

JPS62247697A SIGNAL PROCESSING CIRCUIT FOR TELEVISION RECEIVER 失效
公开(公告)号：JPS62247697A
公开(公告)日：1987-10-28
申请号：JP8991986
申请日：1986-04-21
申请人： HITACHI LTD
发明人： NAKAGAWA HIMIO , MURATA TOSHINORI , HIRAHATA SHIGERU
IPC分类号： H04N11/02 , H04N11/14
摘要： PURPOSE:To reduce necessary memory capacity and to attain a cost reduction by obtaining scan line interpolation signals independently of each other with a luminance signal and a multiplexed luminance signal and applying intra-field interpolation for the scan line interpolation of the multiplexed luminance signal. CONSTITUTION:When the input received from an input terminal 1 is set at a point of time of a scan line 0, the output received from a field memory FM2 is defined as a scan line 262 together with the output received from an FM3 as a scan line 525 and the output received from an FM4 as a scan line 787 respectively. Therefore the luminance signals shifted from each other by the single field time are obtained at the outputs of adders 5 and 7. While the signals obtained by mixing the high band component of the luminance signal and the chiromance signal and having a shift of the single field time are obtained from subtractors 6 and 8. Here the independent scan line interpolation is given to the luminance signal component and the multiplexed luminance signal component respectively. The multiplexed luminance signal component, in particular, undergoes the intra-field interpolation via line memories 15 and 23 and adders 16 and 24.

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