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31. 发明专利

JPH0454653A CACHE MEMORY 失效
公开(公告)号：JPH0454653A
公开(公告)日：1992-02-21
申请号：JP16412190
申请日：1990-06-25
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FURUNOMA TOSHIHIKO , SAIKOU YASUE , KIKUCHI TAKASHI , IWATA MASAKI , SASAKI KOTOKO , FUSE YASUFUMI , HATANO SUSUMU , NISHIMOTO KENJI , AOKI HIROKAZU , NISHII OSAMU
IPC分类号： G06F12/08
摘要： PURPOSE:To shorten the memory access time executed by a processor by allowing a cache memory to share a part of storage information of a main memory and hierarchizing the main memory. CONSTITUTION:A cache memory 3 is provided with an address store part 23, a data memory 24, and a control means 30. In the memory 24, a part of information stored in a main memory 6 is stored, and address information of this information is stored in the stored part 23. Accordingly, by referring to the store contents of this store part 23, whether access object data of a processor MPU 1 exists in the memory 24 or not is known. With respect to an access of the memory 6 from the processor 1, in the case its access object data does not exist in the memory 24 of the inside, a prescribed data group containing its access object data is transferred to the memory 24 form the memory 6. Such a transfer control is executed by a control means 30. In such a way, a system operation stop for initializing a register in the cache memory 3 becomes unnecessary, and the throughput of a cache memory application system is improved.

32. 发明专利

JPH0283895A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH0283895A
公开(公告)日：1990-03-23
申请号：JP23591888
申请日：1988-09-20
申请人： HITACHI LTD
发明人： HATANO SUSUMU , OISHI KANJI
IPC分类号： G11C11/41 , G11C5/00 , H01L27/10
摘要： PURPOSE:To eliminate the overhead of an internal circuit selection by executing the inherent action with an internal circuit based on the instruction from an external part and controlling the internal circuit based on the address information to be held and the address information supplied from the external part. CONSTITUTION:A timing generator 35 of an SRAM 1 receives a bus starting signal to mean the activation of a bus cycle, from external part, and when this is asserted, and starts the internal action of a memory cell array 2 regardless of the fact whether or not the SRAM 1 is the device to be chip-selected. A high order (i) bit out of an address signal ADRS supplied to an external address signal input terminal 3 is the address information which can be assigned for the chip selection of a device and the address information assigned for the chip selection is set to a data register 31. A comparing circuit 30 compares the address information set to the register 31 and (i) bit address information fetched from the external part and based on the compared result, the access of the memory cell array 2 is controlled.

33. 发明专利

JPH023172A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH023172A
公开(公告)日：1990-01-08
申请号：JP14307888
申请日：1988-06-10
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SAIE YASUHIKO , FUKUDA HIROSHI , KIKUCHI TAKASHI , OOISHI KANJI , HATANO SUSUMU , UCHIYAMA KUNIO , AOKI HIROKAZU
IPC分类号： G06F12/08 , G11C11/34 , G11C11/401 , G11C11/413
摘要： PURPOSE:To improve the flexibility of a cache memory by selecting a system to provide a synchronizing circuit in the cache memory and a system composing the synchronizing circuit of an external circuit with a user as needed. CONSTITUTION:When the user constitutes the system so that a cache memory 1 and a main memory can be operated with a same clock, a SYNC signal of an L level is provided from a main storage controller. Then, an inputted MDC (memory bass data complete) signal is not passed through a synchronizing circuit 18 but supplied to a control logic 16. Thus, the processing speed of the system is improved. Next, when the user constitutes the system so that the memory 1 can be operated by the separate clock, the SYNC signal of an H level is given to the memory 1. Then, the MDC signal is passed through a changing-over switch 19 and inputted to the synchronizing circuit 18. Here, the signal goes to be a signal CM, which is synchronized to the clock in the memory 1 side, and the signal is supplied to the logic 16.

34. 发明专利

JP2002123345A BUS SYSTEM 审中-公开
公开(公告)号：JP2002123345A
公开(公告)日：2002-04-26
申请号：JP2001202914
申请日：2001-07-04
申请人： HITACHI LTD
发明人： OSAKA HIDEKI , HATANO SUSUMU , KOMATSU TOYOHIKO , HARA ATSUSHI
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16
摘要： PROBLEM TO BE SOLVED: To make the intervals between memory modules narrow since a certain interval is necessary as the efficiency of transmission, i.e., the degree of coupling, and should not be less than the wiring length that a directional coupler occupies although bus-connected module intervals are determined by the wiring length. SOLUTION: Since a wire (main line) from a memory controller is made to have open ends or short-circuit ends and signals can be generated in both the directions of the directional coupler by using a progressive wave and a reflected wave, DRAMs can be connected to both the sides of the coupler. Consequently, the wiring length of the coupler is reducible to a half of the pitch between modules, so that high-density mounting becomes possible.

35. 发明专利

JP2002044162A DATA TRANSMITTER, DATA TRANSFER SYSTEM AND ITS METHOD 失效
公开(公告)号：JP2002044162A
公开(公告)日：2002-02-08
申请号：JP2000223472
申请日：2000-07-25
申请人： HITACHI LTD
发明人： KOMATSU TOYOHIKO , OSAKA HIDEKI , HORIGUCHI SHINJI , HATANO SUSUMU , ITO KAZUYA
IPC分类号： G06F3/00 , G06F13/42 , H04L12/40 , H04L25/02 , H04L29/08
摘要： PROBLEM TO BE SOLVED: To attain high-speed data transfer on a bus. SOLUTION: A tri-state transmission circuit 101 is shifted from a high impedance state to a data output state, after preset data (dummy data) are transmitted to a bus 1108, substantial data 1107 are sequentially transmitted to the bus 1108. A shortened period of a waveform caused at first data after the transition from the high impedance state to the data output state is caused for the preset data and not caused for the substantial data after the preset data. Thus, a limit in high-speed data transfer due to the shortened period of waveform can be excluded.

36. 发明专利

JP2001027918A DIRECTIONAL COUPLING TYPE MEMORY SYSTEM 失效
公开(公告)号：JP2001027918A
公开(公告)日：2001-01-30
申请号：JP2000126234
申请日：2000-04-20
申请人： HITACHI LTD
发明人： OSAKA HIDEKI , KOMATSU TOYOHIKO , TSUNEHIRO TAKASHI , KIMURA KOICHI , HATANO SUSUMU , ITO KAZUYA , KANNO TOSHIO
IPC分类号： G06F3/00 , G06F1/00 , G06F12/00 , G06F13/16 , H01P5/00 , H01P5/18 , H05K1/00 , H05K1/02 , H05K1/14
摘要： PROBLEM TO BE SOLVED: To narrow a space between memory modules and to improve the packing density of a memory by folding back a main line and constructing a directional coupler to the folded main line. SOLUTION: In regard of the wiring of a main line 1-1, a layer m1 is folded back in the right direction on a drawing when viewed from an MC 10-1 and a wiring layer formed on a mother board 1 is changed into a layer m2 and folded in the left direction on the drawing after the couplers C2, C4, C6 and C8 are constructed to the wirings 1-2, 1-4, 1-6 and 1-8 of a layer c1 which are led from a memory chip. The folded-back line 1-1 constructs the couplers C3, C5, C7 and C9 to the wirings 1-3, 1-5, 1-7 and 1-9 of a layer c2 which are led from the memory chip and then terminated. The couplers C2-C8 are constructed at a position (upper layer) set between the layers m1 and c1 of the board 1, and the couplers C3-C9 are constructed at a position (lower layer) set between the layers m2 and c2 of the board 1 respectively.

37. 发明专利

JP2000011688A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JP2000011688A
公开(公告)日：2000-01-14
申请号：JP18170298
申请日：1998-06-29
申请人： HITACHI LTD
发明人： HATANO SUSUMU , NISHIZAWA HIROTAKA , YAMAGUCHI TOSHIHIRO
IPC分类号： G11C11/403 , G11C11/401 , G11C29/00 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To reduce the power consumption of a dynamic RAM or the like and to increase its product yield in such a way that the access time of the dynamic RAM or the like and the machine cycle of a system containing it are not affected. SOLUTION: An ECC circuit ECC which detects and corrects the error of holding information in units of word lines is installed at a dynamic RAM or the like in which a memory array MARY formed in such a way that memory cells requiring a refresh operation are lattice-arranged is provided and in which a cell refresh mode is provided. When the ECC circuit ECC is set selectively at an operating state only in the cell refresh mode or at the operating mode also in a read mode, an error detection and correction processing operation is executed only to holding information to be rewritten, read-out data or a designated address is output without executing the error detection and correction processing operation.

38. 发明专利

JPH04345994A SEMICONDUCTOR STORAGE AND IMAGE DISPLAY SYSTEM 失效
公开(公告)号：JPH04345994A
公开(公告)日：1992-12-01
申请号：JP14939191
申请日：1991-05-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KIKUCHI TAKASHI , SAIE YASUHIKO , FURUNOMA TOSHIHIKO , SASAKI KOTOKO , HATANO SUSUMU
IPC分类号： G11C7/00 , G11C8/04 , G11C11/401 , G11C11/413
摘要： PURPOSE:To attain the technique that can clear the data at a high speed for each block of a memory cell array in an optional clear pattern. CONSTITUTION:A date input buffer part 14 is provided to fetch the clear data serving as a basic pattern in order to clear a memory cell array 10 for each block in an optional pattern. Meanwhile a data register part 16 generates the batch transfer clear data equivalent to one row of the array 10 based on the output of the part 14 and also transfers the clear data to the array 10. Thus, the date can be cleared at a high speed for each block in an optional clear pattern.

39. 发明专利

JPH04345991A SEMICONDUCTOR STORAGE DEVICE AND PARALLEL COMPUTER SYSTEM 失效
公开(公告)号：JPH04345991A
公开(公告)日：1992-12-01
申请号：JP14939091
申请日：1991-05-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： OOKUBO CHIKAO , KIKUCHI TAKASHI , FUSE YASUFUMI , HATANO SUSUMU
IPC分类号： G06F15/167 , G06F15/16 , G11C11/41
摘要： PURPOSE:To improve the throughput of a computer system. CONSTITUTION:A port control circuit contains the multiplexers 23A-23G and a bidirectional switch 24. The through states can be selectively secured among at least input/output ports 1, 2 mutual internal connection of the optional one of ports 1-3 which can have the individual random accesses to a memory cell array. Thus a triple port memory is applied to a parallel computer system. As a result, the bus neck is eliminated and the system throughput is improved.

40. 发明专利

JPH04281287A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04281287A
公开(公告)日：1992-10-06
申请号：JP6902591
申请日：1991-03-08
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： IWATA MASAKI , KUMAGAI TATSUHIKO , KIKUCHI TAKASHI , SAIE YASUHIKO , HATANO SUSUMU , NISHIMOTO KENJI , KITANO JUN , TAKAHASHI YASUSHI
IPC分类号： G11C11/413 , G11C11/401
摘要： PURPOSE:To exclusively select a writing or a reading operation within a single memory cycle and to write and read within the same memory cycle in parallel by controlling the accessing of a single bus master module. CONSTITUTION:This device is provided with reading/writing circuits of WAMPs 1 to 4, RAMPs 1 to 4, DOBs 1 to 4, DIB 1 to 4, etc., corresponding to each of plural memory cell arrays MCA 1 to 4, the operational modes of the writing/ reading circuits are determined in accordance with control signals LR/W*, UR/W* by which writing/reading operations are divided into the upper and lower sides of the writing/reading circuits and specified. Thus, the writing/ reading operations are carried out within the same cycle and in an optional mode.

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