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31. 发明专利

JPH05190816A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH05190816A
公开(公告)日：1993-07-30
申请号：JP461992
申请日：1992-01-14
申请人： HITACHI LTD
发明人： ITO YUKO , ISOMURA SATORU , SHIMIZU ATSUSHI , YAMADA TAKEO , KOBAYASHI TORU
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52 , H01L27/118
摘要： PURPOSE:To facilitate the logic correction of a semiconductor integrated circuit device. CONSTITUTION:When the wiring layout of a semiconductor integrated circuit device having a multilayer wiring layer is designed, the following steps are performed. At first, all input/output terminals of all logic gates, which are laid out in each chip region of a semiconductor wafer by a plurality of numbers, are lifted up to the uppermost signal wiring layer or to the signal wiring layer immediately beneath the uppermost layer by way of through holes under the state wherein the terminals are arranged in the vertical state as much as possible 101. Then, the layout of the wiring for connecting the logic gates is performed 102.

32. 发明专利

JPH02310966A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02310966A
公开(公告)日：1990-12-26
申请号：JP13132889
申请日：1989-05-26
申请人： HITACHI LTD
发明人： SATO YASUO , KOBAYASHI TORU
IPC分类号： H01L21/3205 , H01L21/82 , H01L21/822 , H01L23/52 , H01L27/04 , H01L27/118 , H03K19/173
摘要： PURPOSE:To enlarge freedom of layout of a rapid digital treatment device, etc., and to enable effective designing of the layout by arranging a terminal resistance between one end of a common connecting wiring arranged serially and a power source voltage or a ground potential of a circuit and by connecting the other end to a second common connecting wiring which is connected with an input terminal of a logic gate circuit at the input side. CONSTITUTION:Output terminals of gates G23, G32, and G42 which constitute a group of a first logic gate circuits are commonly connected through a first common connecting wiring CL1 arranged serially. A negative load resistance which is provided to an output emitter follower circuit of the gate cell G42 is arranged in a node (nc) as a terminal resistance RE which constitutes a connecting logical sum. Meanwhile, after commonly connected through a second common connecting wiring CL2, input terminals of gate cells G16, G27, and G46 which constitute a group of second logic gate circuits are connected to the other end of the common connecting wiring CL1, that is, a branch node (na).

33. 发明专利

JPH0278248A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH0278248A
公开(公告)日：1990-03-19
申请号：JP22865588
申请日：1988-09-14
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： H01L21/82 , G06F1/10 , G06F17/50
摘要： PURPOSE:To stabilize the operations by a method wherein signal lines are periodically coupled with dummy wirings arranged making right angles with the extensions of the signal lines, etc., at the specified intervals. CONSTITUTION:A non-inversion clock-signal line CP 1 and an inversion clock signal line -CP 1 are parallel arranged at the intervals in unit length of (l). The signal lines CP 1 and -CP 1 are respectively coupled with dummy wirings d1-d3 and d4-d6 by a high-speed computer. The dummy wirings in length of 2l are arranged making right angles with the prolonged lines of the clock lines. The values of L and 2l are specified so that any crosstalk noise may be abated even if the general signal wirings are parallel arranged with the clock signal lines. The general signal lines Sa, Sb are arranged close to the complementary clock signal lines. Respective signal lines shall be connected linearly without traversing any other lines at the minimum distance between two connecting points. Through these procedures, the crosstalk noise can be abated while the operations of the high speed computer, etc., can be stabilized, thereby enabling the cycle time to be accelerated equivalently.

34. 发明专利

JPH025453A CONNECTING METHOD FOR MIS CAPACITY 失效
公开(公告)号：JPH025453A
公开(公告)日：1990-01-10
申请号：JP15469388
申请日：1988-06-24
申请人： HITACHI LTD
发明人： YAMADA TOSHIO , KOBAYASHI TORU , NISHIZAWA HIROTAKA , ITOU HIROYUKI , SAITO TATSUYA
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8222 , H01L27/06 , H03K17/60 , H03K19/003
摘要： PURPOSE:To prevent a circuit from erroneously operating by connecting the buried layer side electrode of a MIS(Metal Insulator Semiconductor) capacity to the low impedance side of the circuit. CONSTITUTION:An input VB is connected to the base of a transistor 11, and its emitter side is used as an output VOUT. In order to stabilize an output potential, a MIS capacity 12 is inserted between the output VOUT and a ground potential VCC. In this case, the electrode 13 of the capacity is connected to the output VOUT, and a buried layer side electrode 14 is connected to the potential VCC. Thus, the buried layer side electrode is connected to a low input impedance or a power source side to reduce a potential change due to a noise current and to shorten a potential returning time. Thus, it can prevent a circuit from erroneously operating.

35. 发明专利

JPH01164060A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01164060A
公开(公告)日：1989-06-28
申请号：JP32122787
申请日：1987-12-21
申请人： HITACHI LTD
发明人： YAMADA TOSHIO , KOBAYASHI TORU , TANAKA KAZUO , HAMAMOTO MASATO , IGASHIRA HIROYUKI , SHIMIZU ATSUSHI
IPC分类号： G01R31/28 , G01R31/30 , G06F1/04 , G11C29/00 , G11C29/02 , G11C29/56 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H01L27/118 , H03K19/00
摘要： PURPOSE:To test a saturation margin and an input margin of a gate circuit by a method wherein a bias potential and a reference potential connected to the gate circuit, a memory circuit or the like inside an LSI are changed by an input signal from the outside. CONSTITUTION:This device is constituted by the following: a logic gate part 102 inside a chip 101; a bias-potential generation circuit 103 which feeds a bias potential to the logic gate part; a bias-potential control circuit 104 which changes the bias potential in a step manner. The bias-potential control circuit 104 is connected to the bias-potential generation circuit 103 through a connection 105. In addition, the bias-potential generation circuit 103 feeds the bias potential, a reference potential or the like to the logic gate part 102 through a connection 106. The bias-potential generation circuit 103 changes the bias potential or the like by using a control signal from the bias-potential control circuit 104; it functions in such a way that it maintains an operation margin of a gate circuit 107 within a specified range with respect to a power-supply voltage and a temperature during a normal operation.

36. 发明专利

JPH01157113A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH01157113A
公开(公告)日：1989-06-20
申请号：JP31404487
申请日：1987-12-14
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： H03K19/003 , H03K3/286
摘要： PURPOSE:To reduce an impulsive noise and to stabilize an operation by providing an output emitter follower and a feedback emitter follower for an ECL flip-flop separately, and deteriorating a high frequency characteristic by terminating the feedback emitter follower by a constant current circuit small in current. CONSTITUTION:The ECL flip-flop is constituted of two pairs of differential transistors(TR) T1 and T2, and T3 and T4, etc. To the ECL flip-flop, a first feedback emitter follower(EF) consisting of TRs T5 and T12 and a resistor R3 and a second feedback EF consisting of TRs T6 and T13 and a resistor R4 are coupled. Also, apart from the above, a first output EF is constituted of a TR T7 and a resistor Ry, and a second output EF is constituted of a TR T8 and a resistor R6. At this time, the high frequency characteristic is deteriorated intentionally by terminating the first and second feedback EFs by the load of a constant current source small in current. As a result, it is possible to reduce the impulsive noise due to alpha rays without sacrificing the signal transmission characteristic of the first and second output EFs.

37. 发明专利

JPS6450440A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6450440A
公开(公告)日：1989-02-27
申请号：JP20629587
申请日：1987-08-21
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： H01L21/82 , H03K5/00 , H03K17/60 , H03K19/00 , H03K19/0175
摘要： PURPOSE:To stabilize the operation of a digital information processing device, by selectively cutting the connection wiring between the emitter and the load resistor of a corresponding transistor when an emitter follower circuit is selectively made ineffective, and selectively adding the connection wiring between the collector and the emitter or between the base and the emitter. CONSTITUTION:Connection wirings are provided between the emitters of transistors T5 and T6 and load resistors R5 and R6. Said connection wirings are cut at marks Xs in the Figure. An emitter follower circuit comprising the transistors T5 and T6 is selectively made ineffective. Therefore, a collector capacitor CC5 is equivalently coupled between the base and the collector of the transistor T5. An emitter capacitor Ce5 is equivalently coupled between the base and the emitter of the transistor T5. The same pattern is provided for the transistor T6. Thus the transmission delay time of a bipolar logic circuit becomes approximately constant regardless of the number of the effective emitter follower circuits. Therefore, the operation of a digital information processing device including the bipolar logic circuit is stabilized.

38. 发明专利

JPS63240117A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63240117A
公开(公告)日：1988-10-05
申请号：JP7142787
申请日：1987-03-27
申请人： HITACHI LTD
发明人： HAMAMOTO MASATO , YAMADA TOSHIO , KOBAYASHI TORU
IPC分类号： H03K3/286
摘要： PURPOSE:To contrive the attainment of a stable operation by connecting a common connection emitter (node) of two sets of differential transistors (TRs) being components of an emitter coupling logic (ECL) FF circuit to a prescribed potential point via a leakage resistor. CONSTITUTION:A resistor RL is provided between emitters of common connection of differential transistors T1, T2 of the ECLFF circuit, that is, nodes n1, n2. Parasitic capacitance exists between the nodes n1, n1 and ground and when TRs 3, 6 are transited alternately by a clock CK, the collector current of the TRs 1, 2 or 4, 5 in the on-state is changed. Thus, the base-emitter voltage VBE of the TRs 1, 2 or TRs 4, 5 in the on-state is changed and the parasitic capacitance, i.e., the potential of the nodes n1, n2 tends to be changed, but its change is suppressed by the presence of the RL. Thus, the charge/discharge current of the parasitic capacitance is decreased, the AC noise caused thereby is suppressed and the operation of the ECLFF circuit is stabilized.

39. 发明专利

JPS63122317A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS63122317A
公开(公告)日：1988-05-26
申请号：JP26752586
申请日：1986-11-12
申请人： HITACHI LTD
发明人： SHIOZAWA NOBORU , KOBAYASHI TORU
IPC分类号： H03K19/086
摘要： PURPOSE:To quicken the operating speed of an output circuit by adopting an ECL basic type of one input/one output for an output circuit of a bipolar gate array, adopting a NOR output for the output and connecting a capacitor between a common emitter terminal and a power voltage terminal for a differential input transistor (TR) and a reference TR. CONSTITUTION:Only a NOR output is enabled for an output terminal OUT of an emitter follower EF. Thus, a capacitor Co connected in parallel with constant current sources Qc, Rc acts like a speedup capacitor similarly used in an NTL (non-threshold logic) circuit. Thus, in applying NOR logic for the logic of the output circuit, the capacitor Co acts always like the speedup capacitor. Since only one input TR is in use, there is no TR left as a parasitic capacitor not in use. As a result, the gate delay time is decreased and the operating speed of the output circuit is much quickened.

40. 发明专利

JPS6329178A REFRIGERATOR 失效
公开(公告)号：JPS6329178A
公开(公告)日：1988-02-06
申请号：JP16971186
申请日：1986-07-21
申请人： HITACHI LTD
发明人： YAMAZAKI SUSUMU , MIMORI SADAO , HATANO ISAMU , KOJIMA KANAKO , KOBAYASHI TORU
IPC分类号： F25D11/02

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