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31. 发明专利

JPH01236836A FRAME SYNCHRONIZATION PROTECTING CIRCUIT 失效
公开(公告)号：JPH01236836A
公开(公告)日：1989-09-21
申请号：JP6415688
申请日：1988-03-17
申请人： FUJITSU LTD
发明人： AMAMIYA SHIGEO , KOMINE HIROAKI , SHINOMIYA TOMOHIRO , OTA SHINJI , WATANABE TOSHIAKI
IPC分类号： H04J3/06 , H04L7/08
摘要： PURPOSE:To prevent the erroneous recognition when one frame synchronizing signal detection is missed and to stabilize an action by enlarging the number of steps at a multi-frame mode. CONSTITUTION:A multi-frame instruction signal generating means 32 classifies a multi-frame from a single frame, outputs an instruction signal, a step number variable forward protecting means 33 makes variable the number of forward protecting steps with the instruction signal, and at the time of a single frame, (j) steps are obtained and at the time of the multi-frame, a (k) step more than the (j) times is obtained. Thus, since the number of forward protecting steps is made into k(>j) steps at the multi-frame mode, at the time of the multi-frame, even when one frame synchronizing signal detection is missed due to some reason regardless of the fact that a frame synchronizing signal is present inherently, a (j) times frame synchronizing signal is not detected like the time of a single frame, and the erroneous recognition that it is a pull out is eliminated.

32. 发明专利

JP2000216803A OPTICAL LINE TERMINATING DEVICE AND PON SYSTEM USING THE DEVICE 失效
公开(公告)号：JP2000216803A
公开(公告)日：2000-08-04
申请号：JP1671699
申请日：1999-01-26
申请人： FUJITSU LTD
发明人： SEKIYAMA SHIGEO , SATO HIROYOSHI , AOKI SATORU , HARADA KENJI , SHINOMIYA TOMOHIRO , MIYABE MASATAKE , ABIRU SETSUO , KOYANAGI TOSHINORI , SAKAI TOSHIYUKI
IPC分类号： H04B10/00 , H04B10/272 , H04B10/29 , H04B10/524 , H04B10/556 , H04L12/02 , H04L12/24 , H04L12/26 , H04L12/44 , H04Q3/42 , H04B10/22
摘要： PROBLEM TO BE SOLVED: To realize a measuring processing of delaying time regulated by ITU-T G. 983. SOLUTION: A common part 10 has a starting confirming procedure 12 shifted from a primary state 11 by a starting request from outside, a common setting procedure 13 shifted by issuing a starting confirming request to plural individually corresponding parts and receiving a starting response corresponding to the starting confirming request by the procedure 12, a delay measuring stand-by updating procedure 14 shifted at the time of transmission-controlling a common parameter and finishing the transmission of the common parameter by the procedure 13, and a delay measuring updating procedure 15 updating to the individually corresponding part 20 of the next starting object by issuing the start of the transmission of an individual parameter to the part 20 and receiving the finish of the transmission of an individual parameter by the procedure 14 and shifted after completing update of the part 20 of the starting object.

33. 发明专利

JPH11112568A RING NETWORK BAND ALLOCATING METHOD 失效
公开(公告)号：JPH11112568A
公开(公告)日：1999-04-23
申请号：JP26988697
申请日：1997-10-02
申请人： FUJITSU LTD
发明人： ABIRU SETSUO , SHINOMIYA TOMOHIRO , KUSAYANAGI MICHIO , TAJIMA KAZUYUKI , MIYABE MASATAKE , HIROTA MASAKI , RYU MASAMICHI
IPC分类号： H04L12/42 , H04L12/811 , H04L12/873 , H04L12/911 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To prevent the engrossment of band by a specified node and to share the band of a transmission line by permitting respective nodes to circulate a band request packet onto the transmission line, permitting the nodes to inform all the nodes of a data transmission request state from a terminal through the use of the band request packet and permitting the nodes to independently control transmission in accordance with the data transmission request state. SOLUTION: When the respective nodes #1-#3 generate the band request packtes at prescribed periods in a band request generation part 9 and data is accumulated in a buffer 7 in the self-node, they display band request instructions in the band request packet and transmit it to the transmission line through a multiplexer MUX 8 and a transmitter 10. When the band request packet makes one round of the optical transmission line, it is received by a self-node band request reception part 3, is erased and it is deleted from the transmission line. When a band request detection part 4 receives the band request packet, the respective nodes #1-3 are transmitted to a control part CONT 6 and CONT 6 records the requested node.

34. 发明专利

JPH1168581A CYCLIC REDUNDANCY CHECK CODE REPLACING CIRCUIT 失效
公开(公告)号：JPH1168581A
公开(公告)日：1999-03-09
申请号：JP22256597
申请日：1997-08-19
申请人： FUJITSU LTD
发明人： TAJIMA KAZUYUKI , SHINOMIYA TOMOHIRO , KUSAYANAGI MICHIO , ABIRU SETSUO , MIYABE MASATAKE , HIROTA MASAKI , RYU MASAMICHI
IPC分类号： H03M13/00
摘要： PROBLEM TO BE SOLVED: To reduce a circuit scale by providing an adding means, etc., which uses a cyclic redundancy check code (CRC), that is calculated by an operating means and newly replaces a CRC part on which information is rewritten among the original CRCs that is added to information before rewriting. SOLUTION: When old information is inputted, a latch 11 latches the inputted old information, addresses the latched old information and adds it to a RAM 12a. A 1st gate 13 compares the old information with new information, extracts bits whose values are different, and outputs them to a CRC operating part 2. Then, the part 2 performs 8 bit exclusive-OR processing for every string and acquires an operation result of CRCbit1 to CRCbit8. Also, the value of old CRC that passes through a delaying part 31 is applied to a 2nd gate 33 via a 1st selector 32. With this, the value of the old CRC is compensated in accordance with the operation result of the part 2, a CRC part is replaced with a new CRC value and it is outputted from a 2nd selector 34.

35. 发明专利

JPH1056446A PHASE SELECTION METHOD IN BURST SYNCHRONIZATION CIRCUIT 失效
公开(公告)号：JPH1056446A
公开(公告)日：1998-02-24
申请号：JP21345996
申请日：1996-08-13
申请人： FUJITSU LTD
发明人： HIROTA MASAKI , MIYABE MASATAKE , SHINOMIYA TOMOHIRO , KAWAI MASAAKI , TAJIMA KAZUYUKI , ABIRU SETSUO
IPC分类号： H04J14/08 , H04J3/06 , H04L7/00 , H04L7/10
摘要： PROBLEM TO BE SOLVED: To improve the accuracy of phase selection with respect to burst data. SOLUTION: In this method, an edge is detected by sampling data at a plurality of phase points of burst data in a detection window, and based on the edge detection, a burst synchronization circuit selects a phase with respect to burst data. A phase after a prescribed number such as a phase ϕ3 is selected so as to exclude unstable to parts among selected phases corresponding to a plurality of bits in the edge detection window or a phase with a prescribed number of the same consecutive selected phases is selected or the same phase causing a maximum number of times of the same phases is selected for the selected phase with respect to burst data after the edge detection window.

36. 发明专利

JPH0514397A ROUTE DISTRIBUTING SWITCH FOR ATM CELL 失效
公开(公告)号：JPH0514397A
公开(公告)日：1993-01-22
申请号：JP18294691
申请日：1991-06-27
申请人： FUJITSU LTD
发明人： YAMASHITA HARUO , SHINOMIYA TOMOHIRO , ISHIHARA TOMOHIRO , KONDO RYUICHI , WAKIZAKA TAKAAKI , SUDO TOSHIYUKI
IPC分类号： H04Q3/52 , H04L12/28 , H04Q11/04
摘要： PURPOSE:To prevent the extension of the buffer length and the increase of the internal processing speed in an ATM cell route distributing switch which outputs cells from plural input lines to one desired output line by the ATM transmission system. CONSTITUTION:Numbers of cells staying in buffers where cells are allowed to stay correspondingly to respective input lines INHW of switch elements SW-11 to SW-NN are monitored by an entire read control part CNT and are compared with plural thresholds to read out cells from buffers in the order from the buffer where the number of staying cells exceeds the larger threshold.

37. 发明专利

JPH03105444A MEMORY ADDRESS CONTROL CIRCUIT 失效
公开(公告)号：JPH03105444A
公开(公告)日：1991-05-02
申请号：JP24305789
申请日：1989-09-19
申请人： FUJITSU LTD
发明人： WATANABE TOSHIAKI , SHINOMIYA TOMOHIRO , EZAKI YUTAKA
IPC分类号： G06F12/16
摘要： PURPOSE:To eliminate the round of an abnormal address by storing an idle address and a write address in more than three memories, selecting the address commanding a majority among the addresses and giving them to a data memory or previously correcting the errors of the write/idle addresses so as to set them to be the addresses. CONSTITUTION:The write addresses from a write address generation means 2 are written in common into more than three memories 311-31n in a read address generation means 3 as the read addresses of the data memory 1. If the write addresses change owing to a certain cause, a selection means 32 decides the majority of the addresses, selects one of the majority and gives it to the data memory 1 when the addresses once stored in the memories 311-31n are read as the read addresses by a read control signal. If the address errors occur when the read addresses from the selection means 32 are written in memories 211-21n as the idle addresses, a selection means decides the majority.

38. 发明专利

JPH02292929A ADDRESS CONTROL SYSTEM FOR DATA MEMORY 失效
公开(公告)号：JPH02292929A
公开(公告)日：1990-12-04
申请号：JP11440589
申请日：1989-05-08
申请人： FUJITSU LTD
发明人： EZAKI YUTAKA , SHINOMIYA TOMOHIRO , WATANABE TOSHIAKI , IGUCHI KAZUO , SOEJIMA TETSUO
IPC分类号： G06F12/02 , G06F13/00 , H04L13/08
摘要： PURPOSE:To efficiently use a data memory by providing the data memory where data is held, a FIFO memory where a writable idle address is preserved, and a scheduling memory where addresses are preserved in order. CONSTITUTION:All addresses on a cell preservation RAM (data memory) 1 are stored in a FIFO memory 2. Each time a cell arrives, the write address from the memory 2 is taken out and a data block is written in this address through a write control circuit 3. At this time, the written address is written in a schedule RAM (scheduling memory) 4 also. At the time of reading out data from the RAM 4, the address on the RAN 1 is received from the RAM 4 corresponding to a time pointer 5 for read and data in this address is sent to an exchange switch part of the next stage. Simultaneously, the address read out from the RAM 4 is deleted, and this address is written in the memory 2. That is, the address is returned to the memory 2. Thus, the write address is quickly determined.

39. 发明专利

JPH02271448A ADDRESS CONTROL CIRCUIT 失效
公开(公告)号：JPH02271448A
公开(公告)日：1990-11-06
申请号：JP9357589
申请日：1989-04-13
申请人： FUJITSU LTD
发明人： WATANABE TOSHIAKI , SHINOMIYA TOMOHIRO , EZAKI YUTAKA , SOEJIMA TETSUO , IGUCHI KAZUO
IPC分类号： G06F12/16
摘要： PURPOSE:To inhibit the output by comparing a write address with a read address by a write address comparing means and a read address comparing means, thereby deciding an address value to be abnormal at the time of the discordance. CONSTITUTION:Assuming that a write address 0 (ADR0) from FIFOs 211 and 221 is applied to a comparator 231, the comparator 231 outputs '1' since all bits are coincident with each other. AND gate 232 is turned on, and ADR0 from the FIFO 221 is outputted to a data memory 13 and RAMs 311 and 321. When ADR0 is changed to ADR2 by noise or the like, ADR0 and ADR2 are stored in RAM 311 and 321 respectively. ADR0 and ADR2 are simultaneously outputted to a comparator 331 from RAMs 311 and 321 respectively by an inputted read timing instruction and compared with each other, and the comparator 331 outputs '0' since address values are different from each other. Then, an AND gate 332 is turned off, and ADR2 outputted from the RAM 321 is interrupted.

40. 发明专利

JPH02179141A SWITCH CONTROL SYSTEM 失效
公开(公告)号：JPH02179141A
公开(公告)日：1990-07-12
申请号：JP33136888
申请日：1988-12-29
申请人： FUJITSU LTD
发明人： SHINOMIYA TOMOHIRO , EZAKI YUTAKA , WATANABE TOSHIAKI , IGUCHI KAZUO , SOEJIMA TETSUO
IPC分类号： H04L12/28
摘要： PURPOSE:To improve communication efficiency by controlling plural control buffers storing the storage address of an ATM cell and a speech path switch and an input buffer based on the plural control buffers corresponding to the transmission destination of each input buffer and an asynchronous transfer mode(ATM) cell. CONSTITUTION:When an ATM cell is supplied to an input buffer 111, the storage address of the ATM cell to the input buffer 111 is stored to a control buffer 131 prepared by the output port with the ATM cell sent therefrom corresponding to each input buffer. A 1st control signal 141 reads the storage address data of the input buffer 111 stored respectively to the control buffer 131 in the unit of the output ports, applies the selection to control the speech path switch 121. Moreover, the storage address data of the input buffer 111 selected by the selection is supplied to the corresponding input buffer 111 to read the ATM cell. Thus, since waiting time can be eliminated, the communication efficiency is improved.

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