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1. 发明专利

JPH03117220A PARALLEL/SERIAL CONVERSION SYSTEM 失效
公开(公告)号：JPH03117220A
公开(公告)日：1991-05-20
申请号：JP25585389
申请日：1989-09-29
申请人： FUJITSU LTD
发明人： SATO HIROYOSHI
IPC分类号： H03M9/00
摘要： PURPOSE:To prevent production of an invalid data by providing a storage means, a parallel/serial conversion means and a control means and applying parallel/serial conversion to the remaining data while skipping an invalid data when the invalid data exists in a parallel data. CONSTITUTION:A parallel data inputted from n-set of signal lines is stored in a storage means 10. Then a parallel/serial conversion means 20 extracts the parallel data stored in the storage means 10 sequentially by using a data extraction pulse sent from a control means 30 and converts the extracted data into a serial data. When the means 30 recognizes the absence of data in (a+1)th and succeeding lines among n-sets of signal lines based on bit information, the (a+1)th-n-th pulses in the data extraction pulse generated repetitively in the lines 1-n are skipped. Then the 1st bit of the succeeding period is restored and the parallel/serial conversion is continued. Thus, production of an invalid data is prevented.

2. 发明专利

JPH02184918A FRAME ALIGNING SYSTEM 失效
公开(公告)号：JPH02184918A
公开(公告)日：1990-07-19
申请号：JP560689
申请日：1989-01-12
申请人： FUJITSU LTD
发明人： SATO HIROYOSHI , SUGAWARA AKIRA
IPC分类号： G06F5/06
摘要： PURPOSE:To reduce power consumption and the number of pins for controlling elastic store memory by switching a write pulse to another system when the phase of the write pulse of the system on one side for a readout pulse approaches a phase monitoring range at a phase comparison part. CONSTITUTION:A read reset signal RR is compared with a write reset signal WR, and when both signals enter the phase monitoring range and a timing is set at the one to occur memory slippage, a switching operation to switch a signal to a signal WR2 if a signal WR1 is selected as the signal WR, and to a signal WR1 if the signal WR2 is selected is performed. Therefore, the phase of the signal RR can be deviated from that of the signal WR. In such a way, the power consumption can be reduced compared with a conventional system where two elastic memories are used, and the number of pins for controlling elastic store memory can be reduced.

3. 发明专利

JP2004253854A Method and device for shortening pll pull-in time for srts clock reproduction 有权
公开(公告)号：JP2004253854A
公开(公告)日：2004-09-09
申请号：JP2003039303
申请日：2003-02-18
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO HIROYOSHI , KATO TAKAYUKI
IPC分类号： H04L7/033 , H04L7/08 , H04L12/70
摘要： PROBLEM TO BE SOLVED: To suppress the variation of a constant bit rate signal frequency when changing over from a self-running RTS value running by itself at a nominal frequency to a reception RTS value, with respect to a method and a device for shortening a PLL pull-in time for clock reproduction on a receiver side in an ATM network performing source clock reproduction by using an SRTS system. SOLUTION: In changing over from the self-running RTS value running at the nominal frequency to the reception RTS value, the cycle of a differential frequency of the reception RTS value is detected while the reception RTS value is accumulated in a variation absorbing buffer of a cell delay. In this way, a fixed bit rate signal frequency to be reproduced is roughly predicted, and a self-fluctuating constant bit rate signal frequency which is being generated by the self-running RTS value is previously changed into the predicted reception frequency. COPYRIGHT: (C)2004,JPO&NCIPI

4. 发明专利

JP2001223705A FREQUENCY INFORMATION GENERATING CIRCUIT, FREQUENCY INFORMATION REGENERATING CIRCUIT, AND FREQUENCY INFORMATION TRANSFER, SYSTEM FOR INPUT SIGNAL 失效
公开(公告)号：JP2001223705A
公开(公告)日：2001-08-17
申请号：JP2000031944
申请日：2000-02-09
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO HIROYOSHI , NUIMURA NOBUYUKI , SAKAI TOSHIYUKI , UEMATSU HITOSHI , HIRAMATSU TAICHI , URAHATA SATOYUKI
IPC分类号： H04L7/033 , H04L12/28
摘要： PROBLEM TO BE SOLVED: To provide a frequency information generating circuit and a frequency information regenerating circuit which can shorten a recovery from the break of a CBR signal and the time of synchronism acquisition associated with the break of the CBR signal as to a frequency information generating circuit and a frequency information regenerating circuit for the transmission of a CBR signal asynchronous with the clock signal of an ATM network. SOLUTION: A basic value adding circuit obtains an actual transmit RTS value by finding a basic value by (D-E+C)MOD2p(where MOD2p is operation modulo 2p and C is the standard value of the difference between an RTS value set 1RTS cycle before and a current TRS value) from an RTS value (D) synchronized with the nominal frequency of a network right before a CBR signal recovers and an RTS value (E) synchronized with the CBR signal after the CBR signal recovers and adds the basic value and the RTS value synchronized with the CBR signal after the CBR signal recovers together.

5. 发明专利

JPH1188308A SYNCHRONIZATION SYSTEM FOR FRAME PULSE GENERATION CIRCUIT 失效
公开(公告)号：JPH1188308A
公开(公告)日：1999-03-30
申请号：JP24713997
申请日：1997-09-11
申请人： FUJITSU LTD
发明人： SATO HIROYOSHI , HARADA KENJI , AOKI SATORU
IPC分类号： G06F1/04 , H04L1/22 , H04L7/00
摘要： PROBLEM TO BE SOLVED: To provide the synchronization system of a frame pulse generation circuit for not generating the overlap and omission of data even when a system is switched in the synchronization system of the frame pulse generation circuit for synchronizing the frame pulse generation circuit of a duplexed transmitter. SOLUTION: Duplexed 0 system and 1 system frame pulse generation circuits are provided with a frame pulse generation means 120 for generating frame pulses synchronized with synchronization signals, a synchronization signal judgement means 130 for judging the frame pulses generated by which one of the present system and the other system are to be used as the synchronization signals and a synchronization signal selection means 140 for turning the frame pulses generated by the present system and the other system to input, selecting the frame pulses of the system specified by the output of the synchronization signal judgement means and inputting them to the frame pulse generation means 120. Then, synchronization is attained with the frame pulses generated by the specified present system or the other system as reference.

6. 发明专利

JPH04149896A METHOD FOR CONTROLLING DATA WRITING IN RAM 失效
公开(公告)号：JPH04149896A
公开(公告)日：1992-05-22
申请号：JP27389990
申请日：1990-10-12
申请人： FUJITSU LTD
发明人： SATO HIROYOSHI , SAKAI TOSHIYUKI
IPC分类号： G11C11/413 , G11C11/401 , G11C11/417
摘要： PURPOSE:To reduce the number of RAMs to be used by selecting data read out of a RAM or new data to be written by a data control means and writing the selected data in the RAM to write data consisting of only optional bits. CONSTITUTION:In the case of rewriting the data consisting of optional bits in a specified address of the RAM 10, one address is divided into two addresses, a reading/writing cycle is formed, and after reading out the data of all the bits in the specified address, new data are written. In the case of writing the new data by a data control means 30, new data are selected and old data read out of the same bits are selected and written in the bits in which new data are not written in the RAM 10. Thereby, data writing in optional bits in a specified address of the RAM 10 can be controlled by one write enable signal WE.

7. 发明专利

JPH01321731A DECODER FOR CMI CODE 失效
公开(公告)号：JPH01321731A
公开(公告)日：1989-12-27
申请号：JP15532288
申请日：1988-06-23
申请人： FUJITSU LTD
发明人： SATO HIROYOSHI , OKADA KIMIYOSHI
IPC分类号： H03M5/06 , H04L25/49
摘要： PURPOSE:To eliminate a part dependent upon the transmission speed by latching input data synchronously with a first and second clock signals which have the same speed as transmission of data encoded to the CMI code and are different in phase by 180 deg. and comparing codes of output data. CONSTITUTION:Data encoded to the CMI code is inputted to FFs 3 and 4. The 0-phase clock signal whose transmission speed is equal to that of data encoded to the CMI code is inputted to clock terminals of FFs 3 and 6, and a pi-phase clock signal which is obtained by inverting said 0-phase clock signal by a NOT circuit 7 and is different in phase by 180 deg. is inputted to the clock terminal of the FF 4. A NOT circuit 5 compares both of them with each other and outputs '0' for equal codes and outputs '1' for different codes, and this output is inputted to an FF 6. Since there are no parts dependent upon the transmission speed of data, a general CMI code decoder is obtained.

8. 发明专利

JP2010021655A Power control method and power controller 有权
标题翻译：功率控制方法和功率控制器
公开(公告)号：JP2010021655A
公开(公告)日：2010-01-28
申请号：JP2008178357
申请日：2008-07-08
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO HIROYOSHI
IPC分类号： H04W52/26 , H04W52/28
摘要： PROBLEM TO BE SOLVED: To shorten a period of time needed for the processing of allocating a higher up transmission rate to a base station to the terminal of the higher priority of data transmission.
SOLUTION: In order to allocate the higher up transmission rate to the base station to the terminal of the higher priority of the data transmission, the power controller compares the transmission rate of only the terminal of the transmission priority higher than that of a processing object terminal with the transmission rate of the processing object terminal, and when the transmission rate of the processing object terminal is high, lowers allowable transmission power to the base station from the processing object terminal.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了缩短将数据传输速率较高的传输速率分配给基站至较高数据传输优先级的终端所需的时间。解决方案：为了将更高的传输速率分配给基站到数据传输的较高优先级的终端，功率控制器比较传输优先级的终端的传输速率高于处理对象终端具有处理对象终端的传输速率，并且当处理对象终端的传输速率高时，从处理对象终端降低对基站的可允许传输功率。版权所有（C）2010，JPO＆INPIT

9. 发明专利

JP2008148152A Power allocation method and radio base station system using the same 有权
标题翻译：电力分配方法和使用该方法的无线电基站系统
公开(公告)号：JP2008148152A
公开(公告)日：2008-06-26
申请号：JP2006334944
申请日：2006-12-12
申请人： Fujitsu Ltd , 富士通株式会社
发明人： SATO HIROYOSHI , IIOKA TOSHINORI , SENBA TERUHIKO
IPC分类号： H04B7/26
CPC分类号： H04W52/286 , H04W52/343 , H04W52/346 , H04W52/50
摘要： PROBLEM TO BE SOLVED: To provide a power allocation method which enhances a resending packet reception accuracy at a mobile station in a high speed packet communication and can reduce a retransmission of a packet, and a radio base station system using the same. SOLUTION: The power allocation method for the radio base station system has: a main system for carrying out a usual packet communication between the radio base station system and a plurality of mobile stations; and a sub system for carrying out the high speed packet communication from the radio base station system to the plurality of mobile stations. In this power allocation method, a part of a remaining power obtained by subtracting a using power of the main system from a maximum sending power of the radio base station system is allocated to one mobile station as a sending power of an initial transmission of the high speed packet communication, the sending power is increased by a constant amount more than the power of a previous transmission when the high speed packet communication is resent to the one mobile station, and when the sending power cannot be increased, the using power of the main system is lowered to increase the sending power of the high speed packet communication. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种功率分配方法，其在高速分组通信中提高移动台的重发分组接收精度，并且可以减少分组的重传，以及使用该功率分配方法的无线基站系统。解决方案：无线基站系统的功率分配方法具有：在无线基站系统与多个移动台之间进行通常的分组通信的主系统; 以及用于执行从无线基站系统到多个移动站的高速分组通信的子系统。在该功率分配方法中，通过从无线基站系统的最大发送功率减去主系统的使用功率而获得的剩余功率的一部分被分配给一个移动台作为高速初始传输的发送功率高速分组通信时，当高速分组通信重新发送到一个移动台时，发送功率比先前传输的功率大一个数量级，并且当发送功率不能增加时，主机的使用功率系统降低以增加高速分组通信的发送功率。版权所有（C）2008，JPO＆INPIT

10. 发明专利

JP2002051035A BURST RECEPTION METHOD AND DEVICE 失效
公开(公告)号：JP2002051035A
公开(公告)日：2002-02-15
申请号：JP2000237534
申请日：2000-08-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： SATO HIROYOSHI , KOYANAGI TOSHINORI , SUKEGAWA AYA , WATANABE JUNJI , SASAKI MASAHIRO
IPC分类号： H04J3/06 , H04L7/10 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To provide a burst receiving device consisting of a burst reception section and of a burst reception/synchronization circuit that can secure a normal retiming operation of the burst reception/synchronization circuit even when the burst reception section generates a noise inevitably by its characteristics. SOLUTION: The burst receiving device 1 consisting of the burst reception section 10 and of the burst reception/synchronization circuit 20 is provided with a reception identification signal generating means 31 that outputs a reception identification signal RD denoting that a level of a burst reception data Din received by the burst reception section 10 exceeds a predetermined level and with a mask means 32 that inhibits output burst reception data Bout from the burst reception section 10 to be given to the burst reception/synchronization circuit 20 until at least the reception identification signal generating means 31 outputs the reception identification signal RD.

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