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31. 发明专利

JPS60142439A STORE BUFFER DEVICE 失效
公开(公告)号：JPS60142439A
公开(公告)日：1985-07-27
申请号：JP24610483
申请日：1983-12-29
申请人： FUJITSU LTD
发明人： MORIOKA TETSUYA , TANAKA TSUTOMU , OONISHI KATSUMI , OINAGA YUUJI
IPC分类号： G06F12/00 , G06F12/04 , G06F12/08
摘要： PURPOSE:To remove the interruption of pipe line control by improving the through-put of store in a main storage device. CONSTITUTION:A store buffer device is provided with five store buffers and each store buffer has an upper data register 1 consisting of 8-byte word length, a lower data register 2, a byte mark register 3, and an address register 4. Store data, max. eight bytes each, sent from a central processor 9 every machine cycle are temporarily stored in the registers 1, 2. When data less than eight bytes are written in the upper data register 1, the byte mark register 3 sets up a flag indicating the legality of respective bytes. A selecting circuit 7 selects the upper data register 1 and the lower data register 2. A byte mark forming circuit 8 forms a byte mark to be written in the byte mark register 3 on the basis of the number of store bytes.

32. 发明专利

JPS59177654A Operation by-pass control system 失效
标题翻译：操作旁路控制系统
公开(公告)号：JPS59177654A
公开(公告)日：1984-10-08
申请号：JP5311083
申请日：1983-03-29
申请人： Fujitsu Ltd
发明人： OONO MASAHITO , OONISHI KATSUMI
IPC分类号： G06F9/38
摘要： PURPOSE: To shorten the processing cycle by providing an intermediate register and by-passing the operation result of a preceding instruction, which is established before it is set to an operation result register, from the intermediate register to a succeeding instruction address generating circuit.
CONSTITUTION: Contents of a base register BR1 and an index register XR2 are inputted to an adder 6 through selectors 4 and 5. The output of the adder 6 is stored and controlled by an operand word register OWR8 and is compared with outputs of operand registers 10 and 11 from a register group 14 and is operated in an operating part 12. An intermediate register 13' is provided besides an operation result register 13 in the operating part 12, and the operation result of the preceding instruction which is established before all of the operation result is established is stored in the register 13' and is inputted to selectors 4 and 5 by operation by-pass, and the address of a succeeding instruction is generated by the address generating adder 6. Thus, the processing cycle is shortened.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过提供一个中间寄存器，并将在设置为运算结果寄存器之前建立的前一条指令的运算结果旁路，从中间寄存器到后续指令地址发生电路，缩短处理周期。构成：基本寄存器BR1和索引寄存器XR2的内容通过选择器4和5输入到加法器6.加法器6的输出由操作数字寄存器OWR8存储和控制，并与操作数寄存器10的输出进行比较来自寄存器组14的数据，并且在操作部分12中操作。除了操作部分12中的操作结果寄存器13之外还提供了中间寄存器13'，并且在所有操作部分12之前建立的前一条指令的操作结果操作结果被存储在寄存器13'中，并通过旁路操作被输入到选择器4和5，由地址产生加法器6产生后续指令的地址。因此，处理周期缩短。

33. 发明专利

JPS5955546A Firmware processor 失效
标题翻译：固件处理器
公开(公告)号：JPS5955546A
公开(公告)日：1984-03-30
申请号：JP16606982
申请日：1982-09-24
申请人： Fujitsu Ltd
发明人： KATOU MOTOKAZU , SATOU KIYOSUMI , MIZUSHIMA YOSHIHIRO , OONISHI KATSUMI , MATSUMOTO TOSHIO
IPC分类号： G06F11/00 , G06F9/30 , G06F9/455 , G06F9/48 , G06F11/08
CPC分类号： G06F11/08
摘要： PURPOSE:To process the firmware at a high speed, by providing a control tag for instruction check which can be controlled by firmware, and checking the instruction through various types of instruction check mechanism. CONSTITUTION:For instance, an expanded control register 20 is divided into 16 bits with addition of a control tag 21, and these bits correspond to 16 base registers used for the firmware respectively. An operand part of an instruction fetched from a main storage part or the base register designation information of 4 bits is set to an instruction B part register 24 and then compared with the tag 21 by a comparator 23 through a decoder 25 to be set to a latch circuit 26. The information of the circuit 26 is fed to an AND circuit 30 from an AND circuit 29 while the firmware is used and traveling. While the signal of an instruction code analyzing part 22 is supplied to the circuit 30, and the result of logical arithmetic is delivered to a key check effective/ineffective signal line 11.
摘要翻译：目的：为了高速处理固件，提供可由固件控制的指令检查控制标签，并通过各种指令检查机制检查指令。构成：例如，扩展控制寄存器20通过添加控制标签21被分成16位，这些位分别对应于用于固件的16个基本寄存器。从主存储部分取出的指令的操作数部分或4位的基本寄存器指定信息被设置为指令B部分寄存器24，然后由比较器23通过解码器25与标签21进行比较，以被设置为锁存电路26.当固件被使用和行进时，电路26的信息从AND电路29馈送到AND电路30。当指令代码分析部分22的信号被提供给电路30时，逻辑运算的结果被传送到键检查有效/无效信号线11。

34. 发明专利

JPS593654A History memory control system 失效
标题翻译：历史记忆控制系统
公开(公告)号：JPS593654A
公开(公告)日：1984-01-10
申请号：JP11346482
申请日：1982-06-30
申请人： Fujitsu Ltd
发明人： OONISHI KATSUMI
IPC分类号： G06F9/22 , G06F11/07 , G06F11/14 , G06F11/28 , G06F11/34 , G06F11/36
CPC分类号： G06F11/3636 , G06F11/073 , G06F11/0766 , G06F11/1402 , G06F11/3476 , G06F11/348
摘要： PURPOSE: To set timing precisely, by setting a condition for freezing or resetting a history memory in a microprogram, and controlling the freezing or resetting by said condition and the condition of hardware.
CONSTITUTION: A pipeline consists of an address register AR5, a control memory CS6, and registers TAG0WTAG5, and operations of phases AWF are controlled. A decoder 13 performs normal arithmetic and also outputs indication information X3E or X3F for the freezing or resetting from the program. Further, a freezing or resetting signal SET.FHS or RESET.FHS based upon the hardware condition is inputted to OR circuits 17 or 18, where it is ORed with the signal X3E or X3F to control a latch circuit FHS14. A write enable signal is controlled through an NOR gate 19 by the output of the FHS14 to freeze or reset the contents of the history memory 3. Thus, the timing of the freezing or resetting is set finely.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过设定微型程序中的历史存储器的冻结或复位的条件，以及通过所述条件和硬件条件控制冻结或复位来精确设定时序。构成：管线由地址寄存器AR5，控制存储器CS6和寄存器TAG0-TAG5构成，控制A相F的动作。解码器13执行正常运算，并且还从程序输出用于冻结或重置的指示信息X3E或X3F。此外，基于硬件条件的冻结或复位信号SET.FHS或RESET.FHS被输入到OR电路17或18，其与信号X3E或X3F进行“或”运算以控制锁存电路FHS14。写入使能信号通过FHS14的输出通过NOR门19进行控制，以冻结或复位历史存储器3的内容。因此，精确地设置了冷冻或复位的定时。

35. 发明专利

JPS59739A Time assurance system in microprogram processor 失效
标题翻译：微处理器时间保证系统
公开(公告)号：JPS59739A
公开(公告)日：1984-01-05
申请号：JP11097182
申请日：1982-06-28
申请人： Fujitsu Ltd
发明人： OONISHI KATSUMI , MIZUSHIMA YOSHIHIRO , SATOU KIYOSUMI
IPC分类号： G06F9/22 , G06F9/30 , G06F9/38
CPC分类号： G06F9/30079 , G06F9/223 , G06F9/226 , G06F9/3869
摘要： PURPOSE: To realize the time assurance during microprogram is executed within the mechanics of a microprogram control circuit used normally without using a special circuit.
CONSTITUTION: A loop counting down a preset vaue in an EM field one by one at an ITC register is executed in a dummy cycle. The time required for getting ITC=0 is utilized as the assurance time. The content of an ITCA field at an ITCA register 11 controls the value of the EM field setting from an EM register 12 to an ITC register 20. The content of a PBLC field at a PBLC register 13 performs the control setting a single loop latch 24. When the single latch 20 is set, a valid flag (V) is reset at the end of the PHASE-B.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：实现微程序在通常使用的微程序控制电路的机械结构中执行的时间保证，而不使用特殊电路。构成：在ITC寄存器中逐个逐个计数EM场中的预设值的循环在虚拟循环中执行。获取ITC = 0所需的时间被用作保证时间。 ITCA寄存器11中的ITCA字段的内容控制从EM寄存器12到ITC寄存器20的EM场设置的值。在PBLC寄存器13的PBLC字段的内容执行控制设置单个循环锁存器24 当单个锁存器20被置位时，有效标志（V）在PHASE-B的结尾被复位。

36. 发明专利

JPS584459A ADDRESS COMPARISON SYSTEM IN COMPUTER VARYING ADDRESS MODE 失效
公开(公告)号：JPS584459A
公开(公告)日：1983-01-11
申请号：JP10262281
申请日：1981-06-30
申请人： FUJITSU LTD
发明人： OONISHI KATSUMI , MATSUNOSHITA FUMIO
IPC分类号： G06F9/34 , G06F11/28 , G06F11/36
摘要： PURPOSE:To improve the economy, by eliminating the need for the comparison between a program event recording(PER) start address and a PER end address in each address mode, every time when a specified main storage access event takes place. CONSTITUTION:When an instruction readout event or a main storage renewal event takes place, selectors 1 and 2 select the content of a control register 11 in accordance with an address mode. The output of the selectors 1 and 2 is applied to adders 5 and 6 respectively. The adder 5 calculates the difference between the content transmitted and that of an execution address register 8, and the adder 6 also calculates the difference between the transmitted content and that of the execution register 8. A check circuit 9 checks if an address handled with an instruction readout event or with a main storage renewal event exists between the PER start and end addresses, based on the output of the adders 5 and 6 and + WRAP and AROUND signal.

37. 发明专利

JPS57113146A INSTRUCTION REFETCH SYSTEM 失效
公开(公告)号：JPS57113146A
公开(公告)日：1982-07-14
申请号：JP18907580
申请日：1980-12-29
申请人： FUJITSU LTD
发明人： OONISHI KATSUMI
IPC分类号： G06F9/38
摘要： PURPOSE:To improve processing efficiency by preventing unnecessary instructions from being refetched, by checking the overlap between an instruction prefetch area and a data write area by using variable arithmetic data length stored by a general instruction. CONSTITUTION:When arithmetic data is to be stored in a prefetched-instruction area, an advanced control type high-speed data processor discriminates whether a prefetched instruction needs be refetched or not. In this case, arithmetic data length l stored by a general instruction, prefetched-instruction length Li, the ending address Mi of the prefetched instruction, and the starting address MS of the arithmetic data to be stored are held in registers respectively; the variable values l and Li are processed by addition 9 and an adder 5 finds Mi-Ms-(l+ Li) through complement circuits 4 and 10. Then, its plus or minus sign is detected and when it is plus, the decision 6 is made that the refetching of the instruction is unnecessary. Thus, the variable value (l) is used to check the overlap between the instruction prefetch area and data write area, so the unnecessary instruction refetching is prevented to improve processing efficiency.

38. 发明专利

JPS5696339A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS5696339A
公开(公告)日：1981-08-04
申请号：JP17318879
申请日：1979-12-28
申请人： FUJITSU LTD
发明人： OONISHI KATSUMI
IPC分类号： G06F9/38 , G06F11/00 , G06F11/28 , G06F15/16 , G06F15/177
摘要： PURPOSE:To decide instruction of error occurrence accurately, by reporting the address of the next instruction for detection of the program error when several instructions are transferred from the master processing device to the slave processing device to perform the data processing. CONSTITUTION:When a program error is detected in execution of instruction III, error occurrence is reported to the programmer in the master processing device. The master processing device enters the interrupt cycle due to this reporting. The complement of contents of the first instruction counter 6 and the complement of contents of the second instruction counter 8 are transferred to the second work register 10 and the first work register 9 respectively, and contents of instruction address register 5 and contents of these work registers are added by adder 12, and address 110 of the next instruction is stored in address buffer register 11, and it is reported to the programmer. As a result, the programmer detects that the error occurs in instruction III stored in instruction address 10C just preceding address 110.

39. 发明专利

JPH0823820B2 失效
公开(公告)号：JPH0823820B2
公开(公告)日：1996-03-06
申请号：JP23656685
申请日：1985-10-23
申请人： FUJITSU LTD
发明人： OONO MASAHITO , OONISHI KATSUMI
IPC分类号： G06F9/34 , G06F9/38 , G06F11/00

40. 发明专利

JPH0644245B2 失效
公开(公告)号：JPH0644245B2
公开(公告)日：1994-06-08
申请号：JP24610483
申请日：1983-12-29
申请人： FUJITSU LTD
发明人： MORIOKA TETSUYA , TANAKA TSUTOMU , OONISHI KATSUMI , OINAGA YUUJI
IPC分类号： G06F12/00 , G06F12/04 , G06F12/08
摘要： A digital computer system including a central processing unit CPU (1) ; a main storage unit MSU (4) ; a buffer storage unit (5) functioning as an effective memory device for the CPU with a high speed access time ; and a store buffer device (2) receiving data identical to that to be stored in the buffer storage unit and control information for the received data in response to requests from the CPU and transferring the received data in response and control information to the MSU. The transmission operation from the CPU to the store buffer device and from the store buffer device to the MSU are effected on the basis of a machine cycle timing. The store buffer device (2) includes a controller (29), a plurality of data register sets (21, 22) including data registers for receiving data to be stored in the MSU, a byte mark register set (23) for receiving information indicating storable data in the data registers, and an address register set (24) for receiving a starting store addresss in the MSU for the data to be stored in the data registers.

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