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31. 发明专利

JPH06309275A PREFERENCE SELECTING CIRCUIT 失效
公开(公告)号：JPH06309275A
公开(公告)日：1994-11-04
申请号：JP9322393
申请日：1993-04-20
申请人： FUJITSU LTD
发明人： YAMADA SHIGEKI , OKU TATSUYA , MARUYAMA AKIRA
IPC分类号： G06F13/362
摘要： PURPOSE:To improve the processing speed and to reduce the scale of a preference selecting circuit which selects a single input signal for each of plural slave stations in the multiple processing based on a prescribed preferential condition. CONSTITUTION:An existing choice preferential gate means 1 generates the control data A1-An which invalidated the input signals of younger numbers than a selected one based on the state data D1-Dn which show the valid input signals of a frame and the pre-selection control data B1'-Bn' which show the selected input signals respectively. Then a delay means 2 is added to delay the control data of the means 1 by one bit, together with a gounger number order selection gate means 3 which receives input of the control data delayed by the means 2 and validates only the input signal of the youngest number among those input signals which are valid in the control data, and a dual port RAM means 4 which stores the selection control data B1-Bn and then outputs these data as the data B1'-Bn' in the corresponding time slot of the next frame.

32. 发明专利

JPH01273451A DUPLICATED CLOCK SYNCHRONIZING SYSTEM 失效
公开(公告)号：JPH01273451A
公开(公告)日：1989-11-01
申请号：JP10360488
申请日：1988-04-26
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SHIRAI HIROAKI , NARA KOICHI
IPC分类号： H04L7/033 , G06F1/04 , H04L7/02
摘要： PURPOSE:To synchronize an output clock of a duplicated clock generating circuit by adding a simple gate circuit as a control circuit for a counter. CONSTITUTION:Control circuits 4N, 4E making a count start point for a counter 1N in use and a counter 1E not in use coincident with each other are provided to a clock generating circuit where PLL oscillators 2N, 2E, counters 1N, 1E and decoders 3N, 3E are provided duplicatedly through the gate processing a control signal H of one counter 1N by using the longest period clock in not only a decode output of its own counter 1N but also a decoded output of the other counter 1E. Then the output clocks N, E of the two systems of clock generators are synchronized. Thus, in case of selection and changeover by using a control signal USE deciding which of duplicated clocks is to be used, no data error takes place.

33. 发明专利

JPH01273447A SYNCHRONIZING PATTERN INSERTING METHOD BY LINE SETTING 失效
公开(公告)号：JPH01273447A
公开(公告)日：1989-11-01
申请号：JP10491088
申请日：1988-04-26
申请人： FUJITSU LTD
发明人： NARA KOICHI , SUZUKI SHOJI , MARUYAMA AKIRA
IPC分类号： H04J3/06
摘要： PURPOSE:To make the circuit scale smaller by providing a synchronizing pattern generating section to a line setting common section so as to insert a synchronizing pattern as soon as a line designating plural input data transmission destinations is set. CONSTITUTION:A multiplex section 2 multiplexes plural input data in a line setting common section 1, a memory 3 replaces stored data based on a command from a line setting data generating section 4 and a demultiplex section converts the data into plural output data for the output. The synchronizing pattern generating section 6 generates a required synchronizing pattern for sending it to a transmission destination designating plural output data and inputs it to the memory 3 via the multiplex section 2 together with the plural input data. Then the synchronizing pattern is inserted to a time slot at the head of plural data simultaneously with the replacement of the plural data. Thus, one synchronizing pattern generating section is enough to be provided to the line setting common section 1 and the device is simplified and miniaturized.

34. 发明专利

JPS63155924A MULTIPLEXED DATA TRANSMITTER 失效
公开(公告)号：JPS63155924A
公开(公告)日：1988-06-29
申请号：JP30330186
申请日：1986-12-19
申请人： FUJITSU LTD
发明人： NAKAYAMA SHUNICHI , TAKAHASHI YUJI , MARUYAMA AKIRA
IPC分类号： H04J3/00
摘要： PURPOSE:To multiplex, separate and transmit data of the same quantity as the conventional quantity in data channel parts of the small number by converting the speed of the data of the respective k channels in n channels to that of this data, mutually converting low order multiplex signals arranged for every channel and mutually converting the respective low order multiplex signals to final multiplex signals. CONSTITUTION:The data channel parts 2-1-2-n/k convert in speed the frame data of the cycle tau or the respective k channels in the input and output data 1-1-1-n of the n channels and the data of the respective k channels to the frame of tau/k cycle and mutually convert the low order multiplex signals 3-1-3-n/k sequentially arranged for every channel. A multiplex separating part 4 mutually converts the respective low order multiplex signals 3-1-3-n/k and the final multiplex signals 5. Thereby, since the data channels of the same number as the conventional channels 1a-1h, 2a-h,..., ka-kn,..., na-nh are multiplexed, separated and transmitted, the number of the required data channel parts goes to 1/k of the conventional system.

35. 发明专利

JPS6160015A Decoding system of data 失效
标题翻译：数据解码系统
公开(公告)号：JPS6160015A
公开(公告)日：1986-03-27
申请号：JP18195384
申请日：1984-08-31
申请人： Fujitsu Ltd
发明人： TAKAHASHI YUJI , NAKAYAMA SHUNICHI , MARUYAMA AKIRA
IPC分类号： H03M7/40 , H03M7/30
摘要： PURPOSE: To handle much more information quantity than that of a conventional system while using the same bit number, by receiving a data a part of which is coded as a data address, detecting the data address and reproducing the data content transmitted to a data part other than the data address correspond ingly.
CONSTITUTION: A data inputted in succession to the inputted address is set to a flip-flop 1 in response to a clock signal and fed to decode circuits 3
1 ∼3
4 . The input data is decoded by a decode circuit to which an output signal of latch 4 is applied, e.g., the 3
1 only and 3-bit outputs Y
0 ∼Y
2 are outputted therefrom. When the 3-bit outputs Y
0 ∼Y
2 correspond to a data 001, the outputs Y
0 ∼Y
2 are used as the address for a table of the decoder 6, and 4-bit outputs D'
1 ∼D'
4 to which the data corresponds to 001 are outputted from the said table by using an address 000.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过接收一部分数据被编码为数据地址的数据，处理比常规系统更多的信息量，同时检测数据地址并再现发送到数据部分的数据内容数据地址除外。构成：响应于时钟信号，将连续输入的地址的数据设置到触发器1并馈送到解码电路31-34。输入数据由施加有锁存器4的输出信号的解码电路解码，例如仅输入31，并且从其输出3位输出Y0-Y2。当3位输出Y0-Y2对应于数据001时，输出Y0-Y2用作解码器6的表的地址，4位输出数据对应的D'1-D'4 通过使用地址000从所述表输出到001。

36. 发明专利

JP2004152169A Window switching device and window switching program 有权
标题翻译：窗口切换设备和窗口切换程序
公开(公告)号：JP2004152169A
公开(公告)日：2004-05-27
申请号：JP2002318753
申请日：2002-10-31
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MARUYAMA AKIRA , YAGI TSUTOMU , SEI YOSHIYUKI , IMAIZUMI MINORU , HAYASHI JUNJI , SAITO HIROMI
IPC分类号： G06F3/14 , G06F3/033 , G06F3/048 , G06F9/44 , G06F3/00
CPC分类号： G06F3/0481 , G06F2203/04802
摘要： PROBLEM TO BE SOLVED: To allow a user to easily and rapidly find out and activate a desired window when a plurality of windows are displayed on a screen in a multiplex state. SOLUTION: This window switching device has: a title list display processing part 41 displaying titles of application programs during starting on a screen of a display part 3 as a list; and an activation processing part 42 activating the window of an application program corresponding to a specified title when the desired title is specified through an input part 2. The title list display processing part 41 has: a selection display processing part 41A selecting an a prescribed number of titles and displaying the titles on a title display column of a prescribed size constituting the title list when the number of the application programs during the starting exceeds a prescribed number; and a change display processing part 41B changing and displaying the title displayed as the title list when a title display change command is inputted through the input part 2. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：当在多路复用状态下在屏幕上显示多个窗口时，允许用户容易且快速地找到并激活所需的窗口。该窗口切换装置具有：标题列表显示处理部41，在作为列表的显示部3的画面上显示应用程序的标题; 以及激活处理部分42，通过输入部分2指定期望的标题时，激活对应于指定标题的应用程序的窗口。标题列表显示处理部分41具有：选择显示处理部分41A选择规定数目当起动中的应用程序的数量超过规定数量时，在标题列表的规定尺寸的标题显示列上显示标题，并显示标题; 和变更显示处理部分41B，通过输入部分2输入标题显示改变命令时，改变和显示作为标题列表显示的标题。（C）2004，JPO

37. 发明专利

JPH1051462A MONITOR SYSTEM IN ATM COMMUNICATION DEVICE 失效
公开(公告)号：JPH1051462A
公开(公告)日：1998-02-20
申请号：JP20444896
申请日：1996-08-02
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TATEISHI HIROOMI , TSUJI HIDEO , MARUYAMA AKIRA , WATANABE TOSHIAKI , UEMATSU HITOSHI
IPC分类号： H04Q3/00 , H04L12/26 , H04L12/28 , H04L12/70 , H04L12/931 , H04Q11/04
摘要： PROBLEM TO BE SOLVED: To analyze a fault of a desired path and improve reliability by specifying path discrimination information and inserting a monitor cell, and adding fault information to the monitor cell and outputting them downward. SOLUTION: A monitor cell generation part 2b adds the path discrimination information from a monitor and control part 1 to a header to generate the monitor cell which has its point, sequence number, error detection code, etc., in a payload, and sends it out periodically to a line 5 through a cell insertion part 2d. A monitor part 2a monitors cells on the line and informs the monitor and control part of the number of uninserted cells through an uninserted cell detection part 2c unless there is a vacancy for monitor cell insertion. When a monitor cell detection part 3a detects the monitor cell, a check part 3c checks a reception period, an error, cell loss, passing points, etc., and sends the result to an alarm gathering part 3d. A cell update and generation part 3e updates the monitor cell with gathered alarm information.

38. 发明专利

JPH07264267A TEST CIRCUIT, SELF-TEST METHOD AND USUAL TEST METHOD 失效
公开(公告)号：JPH07264267A
公开(公告)日：1995-10-13
申请号：JP4948994
申请日：1994-03-18
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , AIHARA KOJI
IPC分类号： H03K21/40 , G01R31/3193 , H04L1/22 , H04L7/00 , H04L29/14
摘要： PURPOSE:To attain stable measurement even when an input clock signal having a redundant form is selected in the case of self-monitor by initializing again a synchronization detection circuit when the clock signal is selected and resetting an error counter. CONSTITUTION:A synchronization detection means 230 provides an output of a synchronization establish signal when a test pattern selected by a 1st signal selection means 210 is synchronized with an output pattern from a test signal confirmation means 220 and provides an output of an error signal when out of synchronism is taken. An error counter 240 counts error signals outputted from the synchronization detection means 230. Furthermore, an error counter re-start means 280 monitors a timing when a system of a clock signal received externally is switched and the circuit 230 is set initially within a switching time and when the switching of the system of the clock signal is finished, the counter 240 is reset. Thus, even when the switching of the system clock system takes place during the self-test, the usual test and the self-test are stably continued.

39. 发明专利

JPH06224876A COMMUNICATION PATH MONITORING CIRCUIT 失效
公开(公告)号：JPH06224876A
公开(公告)日：1994-08-12
申请号：JP1214793
申请日：1993-01-28
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , YOSHIDA KATSUMI , KODACHI HIRONORI
IPC分类号： H04J3/12 , H04J3/14 , H04L12/24 , H04L12/26 , H04L29/14
摘要： PURPOSE:To provide the communication path monitoring circuit for respectively recognizing which path of receivers provided with first-Nth transmitters is abnormal. CONSTITUTION:Specified pattern data FTS1-FTSN are inserted to first - Nth data Di1-DiN, which are generated by generating means 34 of first - Nth transmitters 311-31N, by inserting means 35 and transmitted to a receiver 32, one of the specified pattern data FTS1-FTSN inserted to the respective first - Nth data Di1-DiN are passed, the other data are masked corresponding to a select signal SS by a mask means 36, the passed data (such as the FTS 1, for example) are selected corresponding to the signal SS, these selected data FTS 1 are fetched into a check means 38 corresponding to the signal SS so as to check whether those data are normal or abnormal and when they are abnormal, a first alarm signal A1 corresponding to a first path 331 shown by the select signal SS in a present state is outputted.

40. 发明专利

JPH0575670A POWER SUPPLY FAULT DETECTION SYSTEM FOR COMMUNICATION CIRCUIT PACKAGE 失效
公开(公告)号：JPH0575670A
公开(公告)日：1993-03-26
申请号：JP22990391
申请日：1991-09-10
申请人： FUJITSU LTD
发明人： HOSOKAWA TAKAHIRO , YAMAZAKI HIROSHI , OUCHI NOBUAKI , MARUYAMA AKIRA , NARA KOICHI , KIMURA SHUJI , SUZUKI SHOJI
IPC分类号： H04L29/00 , H04L29/14 , H04M3/22
摘要： PURPOSE:To easily detect a fault of an on-board power supply regardless of small power circuit configuration with respect to the power supply fault detection system for the communication circuit package incorporating the on-board power supply in which the power supply circuit is mounted on the board. CONSTITUTION:A supervisory on-board power supply 4 in a supervisory package 6 always supplies a supervisory current I to a communication circuit package 3 and when an output voltage of an on-board power supply 1 has a fault, a voltage fault detection circuit 2 changes the supervisory current I by a prescribed current. When the supervisory current I changes by a prescribed current, a supervisory circuit 5 sends a fault detection signal As to a control package.

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