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    • 34. 发明专利
    • IMAGE PROCESSOR
    • JPS63165974A
    • 1988-07-09
    • JP31340186
    • 1986-12-27
    • YAMAHA CORP
    • YAMAOKA NARIMITSUITO KAZUYUKIIWAMOTO KENJI
    • G06F12/04G06T1/60
    • PURPOSE:To transfer blocks at a high speed by using a means which extracts prescribed continuous bits out of the data to be transferred and produces 1-word data. CONSTITUTION:The source data SD of a transfer destination which is read out of a VRAM for each byte is inputted to a rotator 16 via a latch 11 and a selector 8 to be rotated in response to the bit address of the transfer destination and temporarily latched by an old data latch 17. Then the following read bytes are also rotated by prescribed rotational frequencies and synthesized by a phase mask logic together with the contents of the latch 17. The SD subjected to synthesis is inputted to a mask logic circuit via a logic arithmetic circuit 12 together with the head byte of the transfer destination to be synthesized in accordance with the contents of a mask register MASKO for the head byte of the transfer destination and outputted for each byte to a VRAM of the transferee.