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31. 发明专利

JP2002197892A TEST METHOD FOR SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002197892A
公开(公告)日：2002-07-12
申请号：JP2000396654
申请日：2000-12-27
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KAWAKAMI MASAMI , MIYATA SEISHI , EGUCHI TAKANORI , YAJIMA HIRONOBU , AOKI HIDEYUKI
IPC分类号： G01R31/28 , G11C29/00 , G11C29/44
摘要： PROBLEM TO BE SOLVED: To store data for each cell such as a memory test. SOLUTION: In a test method for a semiconductor device in which measurement is performed for a plurality of cells varying measurement conditions and a plurality of measuring points deciding success or failure of the semiconductor device from obtained data of each cell are set, difference data of data of each cell between continuous measuring points of the plurality of measuring point are obtained, and the difference data are stored. Capacity of stored data is reduced by making the stored data as difference data of data of each cell, and storing data for each cell can be performed.

32. 发明专利

JP2002196980A DATA LOADING METHOD AND DEVICE 审中-公开
公开(公告)号：JP2002196980A
公开(公告)日：2002-07-12
申请号：JP2001325763
申请日：2001-10-24
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YAMAMOTO AKIRA , TSUBOI TOSHIAKI , HONMA SHIGEO , NAKAMURA KATSUNORI , KANBAYASHI KIMISAKI , KITAJIMA HIROYUKI , KURANO AKIRA , NOZAWA MASASHI
IPC分类号： G06F12/08 , G06F3/06
摘要： PROBLEM TO BE SOLVED: To solve the problem that, when an access pattern from a central processing unit to a disk device is changed with time in a same storage region, the using efficiency of a cache memory cannot be held optimally, because the operation mode in the divided and individual storage region of the disk device is fixed. SOLUTION: A disk control device is connected to the disk device and the central processing unit and provided with the cache memory with a physical region on the disk device set to a cache control unit. When no data in a cache control unit including a region to be an access target exists in the cache memory inside, only data in the region to be the access target of the central processing unit is loaded in the cache memory. In this case, when there is an access to data except for those already stored in the cache memory among the data in the cache control unit, the data except for those already stored in the cache memory is loaded in the cache memory.

33. 发明专利

JP2002190532A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JP2002190532A
公开(公告)日：2002-07-05
申请号：JP2000386087
申请日：2000-12-19
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： UENO YOUKI , AKIOKA TAKASHI , MITSUMOTO KINYA , AOYAMA AKIHISA , SHINOZAKI MASAO
IPC分类号： G11C11/41 , G11C7/10 , G11C7/18 , G11C11/419 , H01L21/8244 , H01L27/11
摘要： PROBLEM TO BE SOLVED: To reduce parasitic capacitance formed between a bit line for reading out the signal of a memory cell and a signal transmission line disposed on the upper layer thereof. SOLUTION: Complementary second global bit lines (GBL, /GBL) for transmitting the data of a memory cell MC, read out through complementary bit lines (BL, /BL), are disposed above a memory cell array (BLock). The second global bit line (GBL or /GBL) is disposed, such that an isosceles triangle is defined by connecting the center of cross-section of one complementary bit line (BL), the center of cross-section of the other complementary bit line (/BL), and the center of cross-section of the second global bit line (GBL or /GBL) disposed directly above these complementary bit lines (BL, /BL).

34. 发明专利

JP2002158279A SEMICONDUCTOR IC CIRCUIT AND MANUFACTURING METHOD THEREOF 失效
公开(公告)号：JP2002158279A
公开(公告)日：2002-05-31
申请号：JP2000353326
申请日：2000-11-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SAKAI KENJI , HOTTA KATSUHIKO , SUZUKI NORIO
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To provide a technique which enables to reduce recess generation, prevent the kink phenomenon of MISFET that is formed on an element forming area and reduce leakage current. SOLUTION: After a silicon nitride film 102 is formed on an element forming area of a semiconductor substrate and a slot 104 for element separation is formed by etching an element separation area on the semiconductor substrate, silicon nitride film 106a and a silicon oxide 106b are formed on silicon nitride film 102 containing the slot in this order and polished until the surface of silicon nitride film 102 is exposed. Thus, recess generation can be reduced, because there is silicon nitride film 102 having small etching rate below silicon oxide film 106b. When MISFET is formed on the element forming area, generation of a kink phenomenon can be prevented and the leakage current can be reduced.

35. 发明专利

JP2002158278A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD AND DESIGN METHOD THEREOF 失效
公开(公告)号：JP2002158278A
公开(公告)日：2002-05-31
申请号：JP2000353045
申请日：2000-11-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： KURODA KENICHI , WATABE KOZO , YAMAMOTO HIROHIKO
IPC分类号： H01L21/76 , H01L21/301 , H01L21/304 , H01L21/3105 , H01L21/3205 , H01L21/762 , H01L23/52 , H01L23/528 , H01L27/02 , H01L27/04 , H01L27/08 , H01L27/118
摘要： PROBLEM TO BE SOLVED: To provide a technique which enables to improve flatness of the surface of members buried in concave parts without increasing the time for manufacturing process. SOLUTION: A dummy pattern can be arranged near the boundary BL between an element forming range DA and a dummy area FA by placing in dummy area FA a first dummy pattern DP1 having a relatively large area and a second dummy pattern DP2 having a relatively small area. Thus, flatness of the surface of silicon oxide film that is buried in the separation slot can be improved over the whole area of dummy area FA, and occupying a relatively large area of dummy area FA with first dummy pattern DP1 enables to suppress the increase of the data amount of the mask.

36. 发明专利

JP2002150785A NON-VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JP2002150785A
公开(公告)日：2002-05-24
申请号：JP2000345455
申请日：2000-11-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUZAKI NOZOMI , SHIBA KAZUYOSHI , TANIGUCHI YASUHIRO , TANAKA TOSHIHIRO , SHINAGAWA YUTAKA
IPC分类号： G11C16/06 , G11C8/08 , G11C16/02 , G11C16/12 , G11C16/34
摘要： PROBLEM TO BE SOLVED: To improve convergency and to perform high speed erasure in erasure operation of a non-volatile semiconductor memory. SOLUTION: A word latch circuit is provided for each word line, and threshold value control is performed for each word line in a selection block. The latch circuit shares plural word lines, and occupancy area is reduced. Rewriting voltage is set individually to a completed non-volatile memory, stored in a boot region of the non-volatile memory, and recognizing anew is performed for each a supplying of a power source.

37. 发明专利

JP2002149442A DATA PROCESSOR 失效
公开(公告)号：JP2002149442A
公开(公告)日：2002-05-24
申请号：JP2000342870
申请日：2000-11-10
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUDO AKIRA , MATSUI SHIGESUMI , MATSUMOTO YASUNORI
IPC分类号： G06F11/28 , G06F11/22 , G06F11/36 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a data processor having a debug supporting function capable of monitoring a plurality of kinds of inside buses from the outside part, and identifying the buses being monitored. SOLUTION: A CPU (2), a debug supporting module (9), and the other circuit modules (3, 4, 5, 6) are loaded on a semiconductor chip. The debug supporting module selects an information transmitting path according to a trace condition from among a plurality of information transmitting paths (IAB, IDB, XAB, XDB, YAB, YDB, DAB, DDB) to be used for the operation of the CPU or the like, and holds the trace information obtained according to the trace condition from the selected information transmitting path and the attribute information of the information in a buffer circuit (21), and serially outputs it to the outside part of the semiconductor chip. In this case, it is possible to monitor the plurality of kinds of inside buses from the outside part, and to identify the buses to be monitored. The trace information and the attribute information is serially outputted from the same outside terminal.

38. 发明专利

JP2002149350A DISK DRIVE DEVICE 失效
公开(公告)号：JP2002149350A
公开(公告)日：2002-05-24
申请号：JP2000344699
申请日：2000-11-13
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： YAMATO SATOSHI , TAKAHASHI HIROMASA , MIYAGUCHI YOSHIFUMI
IPC分类号： G06F11/10 , G06F3/06 , G06F9/445 , G06F12/16
摘要： PROBLEM TO BE SOLVED: To securely perform an initialization operation decided in ATAPI specification in short time even by an application program whose program size is large. SOLUTION: In a DVD-ROM disk drive device device, a reboot program RPG, the application program APG1 and an application program APG2 are stored in a flash memory. At the time of starting the application programs APG1 and APG2, the sum value of the application program APG1 is calculated. The calculated value is collated with the previously stored sum value S1. When they are matched, the application program AGP1 is started and the initialization operation is performed. Then, the sum value of the application program APG2 is calculated and the calculated value is collated with the previously stored in the sum value S2. When they are not matched, the application program AGP2 is started.

39. 发明专利

JP2002118621A TRACING METHOD FOR TRANSMISSION-RECEPTION FRAME 失效
公开(公告)号：JP2002118621A
公开(公告)日：2002-04-19
申请号：JP2000311713
申请日：2000-10-05
申请人： HITACHI ULSI SYS CO LTD , HITACHI LTD
发明人： ANZAI ATSUSHI , KODAMA YASUHIRO , OKANO KAORU , ABE SUSUMU , ISE SEIJI
IPC分类号： G06F13/00 , H04L29/14
摘要： PROBLEM TO BE SOLVED: To easily analyze the cause of a network trouble by solving the problem that, although a method in which a transmission-reception frame tracing operation is stopped by a command or the like from a control terminal in such a way that, after the network trouble has been generated, the transmission-reception frame tracing operation is started by the command or the like from the control terminal by waiting for the reappearance of the network trouble is used generally, the method is completely ineffective with reference to the network trouble not reappearing and that a transmission-reception frame cannot be acquired surely in the network trouble due to a delay in the loading of the command. SOLUTION: In order to achieve the purpose, the tracing method is provided with a transmission frame acquisition means (transmission frame tracing means), a reception frame acquisition means (reception frame tracing means), an alarm detection means in the generation of the network trouble and a line trouble detection means in the generation of the network trouble. A transmission-reception frame tracing means is used in such a way that a transmission frame tracing operation and a reception frame tracing operation are stopped by an alarm detection signal and a line trouble tracing signal in the generation of the network trouble and that transmission frame data or reception frame data are retained in the generation of the trouble.

40. 发明专利

JP2002094360A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002094360A
公开(公告)日：2002-03-29
申请号：JP2000284557
申请日：2000-09-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： TSUJI KOSUKE , SATO MITSUMASA , HONDA SHIGERU , SUGANO TOMOHITO , SUZUKI MASATO , MURATA TOMOYASU
IPC分类号： G06F1/06 , G06F5/00 , H03K5/00 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device that can realize high-speed operation and low power consumption by building up a PLL circuit, that employs ring oscillators of a plurality of stages to generate a latch clock signal with a frequency of a plurality of multiple, without multiplying an input clock signal. SOLUTION: A VCO section 52 of the PLL circuit included in an LVDS(low voltage differential signaling) transceiver and an LVDS receiver that is an interface LSI for the LVDS transceiver of a PC body section and the LVDS receiver of a display section in a notebook type personal computer consists of a ring oscillator having 7 stages of inverters IV1-IV7, extracting an output of each stage from each connection node generates 7 phase clock signals at an equal interval, employing the 7 phase clock signals activates each flip-flop of a serial parallel converter, which applies parallel conversion to 7-bit serial signals received in common and each flip-flop extracts 7-bit parallel signals.

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