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1. 发明专利

JP2002007222A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2002007222A
公开(公告)日：2002-01-11
申请号：JP2000188768
申请日：2000-06-23
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUMOTO YASUNORI , MATSUI SHIGESUMI
IPC分类号： G06F12/16 , G06F11/00 , H01L21/82 , H01L21/822 , H01L27/04
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which a specified mask ROM area can be replaced by a RAM area and an alternative RAM area can be substituted for a defective RAM area, even after the mask ROM is manufactured. SOLUTION: A functional part of an LSI of a microcomputer which substitutes for a mask ROM comprises a mask ROM 1, which has four areas sectioned by a specific capacity, an alternative RAM 2 which replaces a prescribed area of the mask ROM 1, an alternative area specifying register 3 which specifies an address for replacing the specific area of the mask ROM 1 with the alternative RAM 2, and an built-in memory control signal generation module 4, which generates a control signal of the mask ROM according to an address of substitution specification and an internal address by access, etc. Access to the mask ROM 1 set to the alternative area specifying register 3 is replaced with the alternative RAM 2.

2. 发明专利

JP2002149442A DATA PROCESSOR 失效
公开(公告)号：JP2002149442A
公开(公告)日：2002-05-24
申请号：JP2000342870
申请日：2000-11-10
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： SUDO AKIRA , MATSUI SHIGESUMI , MATSUMOTO YASUNORI
IPC分类号： G06F11/28 , G06F11/22 , G06F11/36 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a data processor having a debug supporting function capable of monitoring a plurality of kinds of inside buses from the outside part, and identifying the buses being monitored. SOLUTION: A CPU (2), a debug supporting module (9), and the other circuit modules (3, 4, 5, 6) are loaded on a semiconductor chip. The debug supporting module selects an information transmitting path according to a trace condition from among a plurality of information transmitting paths (IAB, IDB, XAB, XDB, YAB, YDB, DAB, DDB) to be used for the operation of the CPU or the like, and holds the trace information obtained according to the trace condition from the selected information transmitting path and the attribute information of the information in a buffer circuit (21), and serially outputs it to the outside part of the semiconductor chip. In this case, it is possible to monitor the plurality of kinds of inside buses from the outside part, and to identify the buses to be monitored. The trace information and the attribute information is serially outputted from the same outside terminal.

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