专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明专利

JP2008177497A Production method of semiconductor device 审中-公开
标题翻译：半导体器件的生产方法
公开(公告)号：JP2008177497A
公开(公告)日：2008-07-31
申请号：JP2007011759
申请日：2007-01-22
申请人： Toshiba Corp , 株式会社東芝
发明人： MATSUSHITA DAISUKE , KATO KOICHI , MITANI YUICHIRO , MURAOKA KOICHI
IPC分类号： H01L21/318 , H01L21/283 , H01L21/8238 , H01L21/8247 , H01L27/092 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To restrain production of an interface defect at the time of forming an insulating film and to reduce the produced defect.
SOLUTION: The method comprises a step of forming a nitride film on the surface of a semiconductor substrate with the semiconductor substrate placed in a first atmosphere containing a first nitriding gas for nitriding the surface of a semiconductor substrate and a first diluting gas substantially unreactive with the semiconductor substrate with the ratio of the sum of the partial pressure of the first diluting gas and the partial pressure of the first nitriding gas and the partial pressure of the first nitriding gas is 5 or more and the total pressure is 40 Torr or less, and a step of forming a first acid nitride layer between the semiconductor substrate and the nitride film and forming a second nitride layer on the surface of the nitride film with the semiconductor substrate having the nitride film formed on the surface placed in a second atmosphere containing an oxidation gas having a bonding energy of the oxygen atom in a range of 1 eV-4 eV and a second diluting gas substantially unreactive with the semiconductor substrate.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了抑制在形成绝缘膜时的界面缺陷的产生并且减少产生的缺陷。解决方案：该方法包括在半导体衬底的表面上形成氮化物膜的步骤，其中半导体衬底放置在含有用于氮化半导体衬底的表面的第一氮化气体的第一气氛和基本上第一稀释气体的分压和第一氮化气体的分压与第一氮化气体的分压的比率与第一氮化气体的分压的比率与半导体衬底不反应，为5以上，总压为40Torr，以及在所述半导体衬底和所述氮化物膜之间形成第一氮化物层并在所述氮化物膜的表面上形成第二氮化物层的步骤，所述半导体衬底具有形成在位于第二气氛中的表面上的所述氮化物膜的所述半导体衬底含有氧原子的氧化气体，所述氧化气体具有在1eV-4eV范围内的氧原子的键合能和基本上与半导体衬底不反应。版权所有（C）2008，JPO＆INPIT

22. 发明专利

JP2008047823A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2008047823A
公开(公告)日：2008-02-28
申请号：JP2006224320
申请日：2006-08-21
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRANO IZUMI , MITANI YUICHIRO , MATSUSHITA DAISUKE , SAKUMA KIWAMU , NAKASAKI YASUSHI , KATO KOICHI , FUKATSU SHIGETO , MURAOKA KOICHI
IPC分类号： H01L29/78 , H01L21/316
摘要： PROBLEM TO BE SOLVED: To improve long-term reliability of a semiconductor device which uses a metal oxide film or a metal silicon oxide film for a gate insulating film.
SOLUTION: The manufacturing method of the semiconductor device using a high dielectric constant gate insulating film forms a silicon oxide film 21 on a semiconductor substrate 10, and thereafter forms an aluminum film 25 on the silicon oxide film 21. Then, the method subsequently forms the high dielectric constant gate insulating film 24 having a high dielectric constant gate insulating film having a dielectric constant higher than that of the silicon oxide film 21 on the aluminum film 25, introduces nitride into the gate insulating film 24, forms a gate electrode material film on the gate insulating film 24, and processes the gate electrode material film to be a gate pattern to form gate electrode 30.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了提高使用金属氧化物膜或金属氧化硅膜作为栅极绝缘膜的半导体器件的长期可靠性。解决方案：使用高介电常数栅极绝缘膜的半导体器件的制造方法在半导体衬底10上形成氧化硅膜21，然后在氧化硅膜21上形成铝膜25.然后，该方法随后形成具有介电常数高于铝膜25上的氧化硅膜21的介电常数高介电常数栅极绝缘膜的高介电常数栅极绝缘膜24，将氮化物引入栅极绝缘膜24中，形成栅电极栅极绝缘膜24上的材料膜，并且将栅电极材料膜加工成栅极图案以形成栅极30.版权所有（C）2008，JPO＆INPIT

23. 发明专利

JP2007053392A Method of manufacturing mis field effect transistor and method of manufacturing semiconductor memory device 审中-公开
标题翻译： MIS场效应晶体管的制造方法和制造半导体存储器件的方法
公开(公告)号：JP2007053392A
公开(公告)日：2007-03-01
申请号：JP2006270742
申请日：2006-10-02
申请人： Toshiba Corp , 株式会社東芝
发明人： YAMAGUCHI TAKESHI , MITANI YUICHIRO , SATAKE HIDEKI , FUKUSHIMA SHIN
IPC分类号： H01L29/78 , H01L21/316 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing an MIS field effect transistor using a metal oxide the defect of which is hardly caused and which has high resistance to hydrogen and water as a gate insulating film.
SOLUTION: A method of manufacturing an MIS field effect transistor comprises processes of: forming a metal oxide film on a silicon substrate; forming a gate electrode on the metal oxide film; and introducing fluorine into the metal oxide film. A Hf oxide or an Al oxide is used as the metal oxide film. For example, an introduction of fluorine into the metal oxide film is performed by introducing fluorine or ions including fluorine into the silicon substrate prior to formation of the metal oxide film on the silicon substrate, and then by heat-treating the silicon substrate after forming the metal oxide film in order to diffuse fluorine from the silicon substrate into the metal oxide film.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造MIS场效应晶体管的方法，所述MIS场效应晶体管使用金属氧化物，其缺陷几乎不引起，并且具有高的耐氢和水作为栅极绝缘膜的能力。解决方案：制造MIS场效应晶体管的方法包括以下处理：在硅衬底上形成金属氧化物膜; 在所述金属氧化物膜上形成栅电极; 并将氟引入到金属氧化物膜中。使用Hf氧化物或Al氧化物作为金属氧化物膜。例如，通过在硅衬底上形成金属氧化物膜之前，将氟或含氟离子引入到硅衬底中，然后通过在形成硅衬底之后对硅衬底进行热处理，将氟引入到金属氧化物膜中金属氧化物膜，以便将氟从硅衬底扩散到金属氧化物膜中。版权所有（C）2007，JPO＆INPIT

24. 发明专利

JP2006005006A Nonvolatile semiconductor memory 审中-公开
标题翻译：非易失性半导体存储器
公开(公告)号：JP2006005006A
公开(公告)日：2006-01-05
申请号：JP2004177191
申请日：2004-06-15
申请人： Toshiba Corp , 株式会社東芝
发明人： NARA AKIKO , KOIKE MASAHIRO , MITANI YUICHIRO
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/105 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28194 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/513 , H01L29/517 , H01L29/7883
摘要： PROBLEM TO BE SOLVED: To reduce a leakage current even in either high electric field of both a positive electrode and a negative electrode, and to inhibit the leakage current in a wide electric-field range from a low electric field to a high electric field difficult in a single high dielectric film.
SOLUTION: A nonvolatile semiconductor memory comprises a floating gate electrode 12 selectively formed on the main surface of a first conductivity type semiconductor substrate 10 through a tunnel insulating film 11, and a control gate electrode 14 formed on the floating gate electrode 12 through an inter-electrode insulating film 13. The nonvolatile semiconductor memory further has second conductivity type source-drain regions 15 formed on the main surface of the substrate in response to each gate electrode 12 and 14. In the nonvolatile semiconductor memory, the inter-electrode insulating film 13 has three layers or more of a laminated structure composed of two kinds or more of high dielectric materials 13a, 13b and 13c.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使在正电极和负电极的高电场中也能够减小漏电流，并且在从低电场到高电平的宽电场范围内抑制泄漏电流电场难以在单个高介电膜中。解决方案：非易失性半导体存储器包括通过隧道绝缘膜11选择性地形成在第一导电类型半导体衬底10的主表面上的浮栅电极12和形成在浮栅电极12上的控制栅极14 电极间绝缘膜13.非易失性半导体存储器还具有响应于每个栅电极12和14形成在基板的主表面上的第二导电型源极 - 漏极区域15.在非易失性半导体存储器中，绝缘膜13具有由两种以上的高介电材料13a，13b，13c构成的层叠结构的三层以上。版权所有（C）2006，JPO＆NCIPI

25. 发明专利

JP2015061201A 個体識別装置、記憶装置、個体識別システム、その方法、およびプログラム有权
标题翻译：个人识别设备，存储设备，个体识别系统，其方法和程序
公开(公告)号：JP2015061201A
公开(公告)日：2015-03-30
申请号：JP2013193542
申请日：2013-09-18
申请人：株式会社東芝 , Toshiba Corp
发明人： CHEN JIEZHI , MITANI YUICHIRO , TANAMOTO TETSUFUMI , MARUGAME TAKAO
IPC分类号： H04L9/10 , G06F21/62 , G06F21/73 , G11C16/02 , G11C16/04
CPC分类号： G06F3/0631 , G06F3/0604 , G06F3/0622 , G06F3/0637 , G06F3/0688 , G06F21/73 , H04L9/0866 , H04L9/3278
摘要：【課題】複製困難な物理的特徴を具備する素子ばらつきを利用した個体識別を行う。【解決手段】実施形態にかかる個体識別装置は、1つ以上のメモリチップを含む記憶装置を個体識別する個体識別装置であって、書込データを記憶する第1記憶部と、前記書込データを各メモリチップの所定の領域に書き込む領域指定部と、前記書込データと各メモリチップの前記所定の領域から読み出した読出データとのミスマッチビットから指紋データを生成する指紋生成部とを備える。【選択図】図1
摘要翻译：要解决的问题：使用不重复的物理特征的元素变化来执行个体识别。解决方案：执行包含一个或多个存储器芯片的存储设备的单独标识的单独识别装置包括：存储写入的第一存储部件数据; 写入数据在每个存储芯片的预定区域中的区域指定部分; 以及指纹生成部，其从写入数据中的不匹配位和从每个存储芯片的预定区域读出的读出数据生成指纹数据。

26. 发明专利

JP2014120735A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2014120735A
公开(公告)日：2014-06-30
申请号：JP2012277254
申请日：2012-12-19
申请人： Toshiba Corp , 株式会社東芝
发明人： HIRANO IZUMI , MITANI YUICHIRO , MIYATA MASAYASU , NAKASAKI YASUSHI , KATO KOICHI , MATSUSHITA DAISUKE , TAKASHIMA AKIRA , MOROTA MISAKO
IPC分类号： H01L27/115 , H01L21/336 , H01L21/8247 , H01L29/788 , H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L21/28282 , H01L27/11521 , H01L27/11556 , H01L29/42332 , H01L29/511 , H01L29/7881 , H01L29/7889
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having high reliability as a memory cell.SOLUTION: A nonvolatile semiconductor memory device includes: a semiconductor region; a first insulating film provided on the semiconductor region; a charge storage film provided on the first insulating film; a hydrogen diffusion prevention film provided on the charge storage film; a second insulating film provided on the hydrogen diffusion prevention film; a control gate electrode provided on the second insulating film; a hydrogen emission film provided on the control gate electrode; and side walls provided on side surfaces of a laminated structure including the first insulating film, the charge storage film, the hydrogen diffusion prevention film, the second insulating film, and the control gate electrode, and containing a material that prevents diffusion of hydrogen.
摘要翻译：要解决的问题：提供具有高可靠性的非易失性半导体存储器件作为存储单元。解决方案：非易失性半导体存储器件包括：半导体区域; 设置在所述半导体区域上的第一绝缘膜; 设置在所述第一绝缘膜上的电荷存储膜; 设置在电荷存储膜上的氢扩散防止膜; 设置在氢扩散防止膜上的第二绝缘膜; 设置在所述第二绝缘膜上的控制栅电极; 设置在控制栅电极上的氢发射膜; 以及设置在包括第一绝缘膜，电荷存储膜，氢扩散防止膜，第二绝缘膜和控制栅电极的层叠结构的侧表面上的侧壁，并且包含防止氢扩散的材料。

27. 发明专利

JP2013157444A Non-volatile resistance change element, writing method, and non-volatile memory 审中-公开
标题翻译：非易失性电阻变化元件，写入方法和非易失性存储器
公开(公告)号：JP2013157444A
公开(公告)日：2013-08-15
申请号：JP2012016724
申请日：2012-01-30
申请人： Toshiba Corp , 株式会社東芝
发明人： CHEN JIEZHI , MATSUZAWA KAZUYA , MITANI YUICHIRO
IPC分类号： H01L27/105 , G11C13/00 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To suppress operation variations.SOLUTION: A non-volatile resistance change element according to the present embodiment includes: a first electrode; a second electrode containing a metal element; a variable resistance layer provided between the first electrode and the second electrode; insulating films provided on at least one pair of side surfaces facing each other of the variable resistance layer; and third electrodes which are provided on the one pair of side surfaces facing each other of the variable resistance layer so as to sandwich the insulating films therebetween.
摘要翻译：要解决的问题：抑制操作变化。解决方案：根据本实施例的非易失性电阻变化元件包括：第一电极; 含有金属元素的第二电极; 设置在所述第一电极和所述第二电极之间的可变电阻层; 提供在可变电阻层的彼此相对的至少一对侧表面上的绝缘膜; 以及设置在可变电阻层的彼此面对的一对侧表面上以将绝缘膜夹在其间的第三电极。

28. 发明专利

JP2010122055A Method, apparatus and program for evaluating semiconductor device 审中-公开
标题翻译：用于评估半导体器件的方法，装置和程序
公开(公告)号：JP2010122055A
公开(公告)日：2010-06-03
申请号：JP2008295718
申请日：2008-11-19
申请人： Toshiba Corp , 株式会社東芝
发明人： FUKATSU SHIGETO , MITANI YUICHIRO , HAGISHIMA DAISUKE , MATSUZAWA KAZUYA , INOUE KOICHIRO
IPC分类号： G01R31/26 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a method, apparatus and program for evaluating a semiconductor device, capable of simply estimating a reliability lifetime more accurately in comparison with conventional those.
SOLUTION: The method includes: a stress voltage applying step S42 of applying a stress voltage to a gate electrode of a PMOS transistor for a fixed time; a measuring step S43 of measuring drain current Id after an elapse of the fixed time; a recovery voltage applying step S45 of applying a recovery voltage whose absolute value is smaller than that of the stress voltage, to the gate electrode for a second fixed time; a measuring step S46 of measuring drain current Id after an elapse of the second fixed time; an approximating step of obtaining an approximation expression for approximating a relation between a drain current degradation rate ΔId and an operation time, based on the drain current Id measured by the measuring step S43 and the drain current Id measured by the measuring step S46; and a calculating step of calculating the reliability lifetime, by substituting a numerical value which is a criteria of the reliability lifetime, in the drain current degradation rate ΔId of the approximation expression.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于评估半导体器件的方法，装置和程序，其能够比传统的那些更准确地估计可靠性寿命。解决方案：该方法包括：施加应力电压至PMOS晶体管的栅电极一定时间的应力电压施加步骤S42; 在经过固定时间之后测量漏极电流Id的测量步骤S43; 恢复电压施加步骤S45，将绝对值小于应力电压的恢复电压施加到栅电极第二固定时间; 测量步骤S46，测量经过第二固定时间之后的漏极电流Id; 基于由测量步骤S43测量的漏极电流Id和通过测量步骤S46测量的漏极电流Id，获得用于近似漏极电流劣化率ΔId和操作时间之间的关系的近似表达式的近似步骤; 以及通过将作为可靠寿命的标准的数值代入近似表达式的漏极电流劣化率ΔId来计算可靠性寿命的计算步骤。版权所有（C）2010，JPO＆INPIT

29. 发明专利

JP2010085354A Method for evaluating semiconductor device, evaluating device and evaluation program 审中-公开
标题翻译：评估半导体器件，评估器件和评估程序的方法
公开(公告)号：JP2010085354A
公开(公告)日：2010-04-15
申请号：JP2008257268
申请日：2008-10-02
申请人： Toshiba Corp , 株式会社東芝
发明人： SHODA AKIKO , MITANI YUICHIRO , HIRANO IZUMI , FUKATSU SHIGETO
IPC分类号： G01R31/26
摘要： PROBLEM TO BE SOLVED: To accurately determine a hot carrier deterioration lifetime of a field effect transistor.
SOLUTION: A method for evaluating a semiconductor device includes: a first application step S1301 for applying at least two voltages to a gate electrode for a predetermined time; a first measurement step S1302 for measuring a first gate current density and a first deterioration amount caused by bias temperature instability; an approximation step S1304 for determining an approximation equation of the deterioration amount of a semiconductor and the current density of the gate electrode based on the first deterioration amount and the first gate current density; a second application step S1305 for applying a voltage to the gate electrode and a drain electrode for a predetermined time; a second measurement step S1306 for measuring a second gate current density and a second deterioration amount caused by hot carrier; a first calculation step S1307 for calculating a third deterioration amount that is a bias temperature instability component of the second deterioration amount from the approximation equation; and a second calculation step S1308 for calculating a fourth deterioration amount that is a hot carrier component of the second deterioration amount from the second and third deterioration amounts.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：准确地确定场效应晶体管的热载流子劣化寿命。解决方案：一种用于评估半导体器件的方法包括：第一施加步骤S1301，用于将至少两个电压施加到栅电极达预定时间; 用于测量由偏置温度不稳定性引起的第一栅极电流密度和第一劣化量的第一测量步骤S1302; 基于第一劣化量和第一栅极电流密度，确定半导体的劣化量的近似方程和栅电极的电流密度的近似步骤S1304; 第二施加步骤S1305，用于向栅电极和漏电极施加预定时间的电压; 用于测量由热载体引起的第二栅极电流密度和第二劣化量的第二测量步骤S1306; 第一计算步骤S1307，用于根据近似等式计算作为第二劣化量的偏置温度不稳定性分量的第三劣化量; 以及第二计算步骤S1308，用于从第二和第三劣化量计算作为第二劣化量的热载体分量的第四劣化量。版权所有（C）2010，JPO＆INPIT

30. 发明专利

JP2010010349A Nonvolatile semiconductor storage device, and manufacturing method of the same 审中-公开
标题翻译：非挥发性半导体存储器件及其制造方法
公开(公告)号：JP2010010349A
公开(公告)日：2010-01-14
申请号：JP2008167281
申请日：2008-06-26
申请人： Toshiba Corp , 株式会社東芝
发明人： ITO TOSHIHIDE , TSUCHIYA YOSHINORI , SAKAMOTO WATARU , MITANI YUICHIRO , KOYAMA MASATO
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device with a memory cell having an appropriate threshold voltage regardless of use of a metal material of high process matching property for a control gate electrode, and to provide a manufacturing method thereof.
SOLUTION: The device includes a semiconductor substrate 1, source and drain regions 4a, 4b disposed on the semiconductor substrate apart from each other, a first insulating film 12 formed on a part serving as a channel region 6 between the source and drain regions on the semiconductor substrate, a charge accumulation film 13 formed on the first insulating film, a second insulating film 14 formed on the charge accumulation film and the control gate electrode 18 formed on the second insulating film and containing at least any one of the elements selected from the group of Ni, Co, Pd and Pt, and Si and O.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种具有适当阈值电压的存储单元的非易失性半导体存储装置，而不管使用控制栅电极的高工艺匹配性能的金属材料，并提供其制造方法。解决方案：该器件包括半导体衬底1，设置在半导体衬底上的源极和漏极区域4a，4b，形成在用作源极和漏极之间的沟道区域6的部分上的第一绝缘膜12 半导体基板上的区域，形成在第一绝缘膜上的电荷累积膜13，形成在电荷累积膜上的第二绝缘膜14和形成在第二绝缘膜上的控制栅电极18，并且包含至少任一个元件选自Ni，Co，Pd和Pt，Si和O组。版权所有（C）2010，JPO＆INPIT

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式