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21. 发明专利

JP2011258284A Resistance control method for nonvolatile variable resistance element 有权
标题翻译：电阻可变电阻元件的电阻控制方法
公开(公告)号：JP2011258284A
公开(公告)日：2011-12-22
申请号：JP2010133016
申请日：2010-06-10
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0007 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0083 , G11C2013/0088 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a resistance control method for a nonvolatile variable resistance element that allows a plurality of memory cells to be written, erased, and forming processed simultaneously.SOLUTION: A nonvolatile semiconductor memory device includes a memory cell array where unit memory cells each having a nonvolatile variable resistance element and a transistor in a matrix, and a memory operation object memory cell is selected by first selection lines (word lines), second selection lines (bit lines), and a third selection line (source line). In the nonvolatile semiconductor memory device, a resistance control method for a nonvolatile variable resistance element includes a step of selecting one or more first selection lines, a step of selecting a plurality of second selection lines, and a step of applying voltages to a voltage necessary for memory operation that compensates a potential variation of the third selection line resulted from the current flows through the second selection lines to the third selection line in order to apply the necessary voltage for memory operation to all the selected memory cells.
摘要翻译：要解决的问题：提供一种允许同时写入，擦除和形成多个存储单元的非易失性可变电阻元件的电阻控制方法。解决方案：非易失性半导体存储器件包括存储单元阵列，其中每个具有易失性可变电阻元件和矩阵中的晶体管的单元存储单元和存储器操作对象存储单元由第一选择线（字线）选择，，第二选择线（位线）和第三选择线（源极线）。在非易失性半导体存储器件中，用于非易失性可变电阻元件的电阻控制方法包括选择一个或多个第一选择线，选择多个第二选择线的步骤和向所需电压施加电压的步骤用于存储器操作，其补偿由电流流过第二选择线到第三选择线所产生的第三选择线的电位变化，以便将所需的存储器操作电压施加到所有选定的存储器单元。版权所有（C）2012，JPO＆INPIT

22. 发明专利

JP2011248953A Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：JP2011248953A
公开(公告)日：2011-12-08
申请号：JP2010119948
申请日：2010-05-26
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA , NAGURA MITSURU , OTA YOSHIJI
IPC分类号： G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105
CPC分类号： G11C7/12 , G11C8/08 , G11C13/0004 , G11C13/0007 , G11C13/0026 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of suppressing write disturbance without increasing area of a cell array.SOLUTION: A semiconductor memory device comprises a memory cell array 100 in which a plurality of memory cells each having a two-terminal type memory element R and a selection transistor Q connected in series are arranged in a matrix; a first voltage application circuit 101 for applying a rewriting voltage pulse to a first bit line; and a second voltage application circuit 102 for applying precharge voltage to a first and a second bit lines. In the semiconductor memory device, at a time of rewriting a memory cell, after the second voltage application circuit 102 precharges both ends of the memory cell to the same voltage in advance, the first voltage application circuit 101 applies the rewriting voltage pulse through the first bit line directly connected to the selection transistor, and the second voltage application circuit 102 applies the precharge voltage to the second bit line connected directly to the memory element.
摘要翻译：解决的问题：提供能够抑制写入干扰而不增加单元阵列的面积的半导体存储器件。解决方案：半导体存储器件包括：存储单元阵列100，其中分别具有两端型存储元件R和串联连接的选择晶体管Q的多个存储单元布置成矩阵; 用于将重写电压脉冲施加到第一位线的第一电压施加电路101; 以及用于向第一和第二位线施加预充电电压的第二电压施加电路102。在半导体存储器件中，在重写存储单元时，在第二电压施加电路102预先将存储单元的两端预先充电到相同的电压之后，第一电压施加电路101通过第一电压施加电路施加重写电压脉冲直接连接到选择晶体管，并且第二电压施加电路102将预充电电压施加到直接连接到存储元件的第二位线。版权所有（C）2012，JPO＆INPIT

23. 发明专利

JP2011065745A Nonvolatile semiconductor memory device and method of controlling the same 有权
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：JP2011065745A
公开(公告)日：2011-03-31
申请号：JP2010244891
申请日：2010-11-01
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA , ISHIKAWA YUTAKA , OTA KEIJI
IPC分类号： G11C13/00 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which achieves a high-speed rewrite operation to memory cells. SOLUTION: The device includes: a memory cell array including first and second sub-banks formed by arranging a plurality of nonvolatile memory cells in a matrix; a row decoder common to the first and second sub-banks; first and second column decoders provided for the first sub-bank and the second sub-bank, respectively; and a control circuit which alternately carries out a first operation cycle in which a write operation to the first sub-bank and a read operation for a write verifying operation to the second sub-bank are performed, and a second operation cycle in which a read operation for a write verifying operation to the first sub-bank and a write operation to the second sub-bank are performed. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种对存储单元实现高速重写操作的非易失性半导体存储器件。解决方案：该装置包括：存储单元阵列，包括通过以矩阵形式布置多个非易失性存储单元而形成的第一和第二子库; 第一和第二子库共同的行解码器; 分别为第一子行和第二子行设置的第一和第二列解码器; 以及控制电路，其交替地执行第一操作周期，其中执行对第一子库的写入操作和对第二子存储体的写入验证操作的读取操作，以及第二操作周期，其中读取执行对第一子库的写入验证操作和对第二子组的写入操作。版权所有（C）2011，JPO＆INPIT

24. 发明专利

JP2010218603A Control circuit for forming process on nonvolatile variable resistive element and control method for forming process 有权
标题翻译：用于形成非易失性电阻元件的控制电路和控制方法
公开(公告)号：JP2010218603A
公开(公告)日：2010-09-30
申请号：JP2009061771
申请日：2009-03-13
申请人： Sharp Corp , シャープ株式会社
发明人： KAWABATA MASARU , ISHIHARA KAZUYA , OTA KEIJI
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0007 , G11C13/0011 , G11C13/0064 , G11C13/0069 , G11C2013/0083 , G11C2213/34 , G11C2213/72 , G11C2213/79 , H01L27/24
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device carrying out a forming process simultaneously on the nonvolatile variable resistive elements of a plurality of memory cells and shortening a forming period. SOLUTION: The nonvolatile semiconductor memory device includes a forming detection circuit 510 provided between a memory cell array 501a and a second selection line (bit line) decoder 508. The forming detection circuit 510 detects a completion of the forming process of each memory cell by measuring a potential fluctuation of the second selection lines or a current amount flowing through the second selection lines when applying a voltage pulse for the forming process through the second selection lines to a plurality of memory cells on which the forming process is to be carried out connected to same first selection line (word line), and a control to prevent a voltage from being applied to the second selection lines connected to the memory cell where the completion of the forming process is detected. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种在多个存储单元的非易失性可变电阻元件上同时执行形成处理并且缩短形成周期的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括设置在存储单元阵列501a和第二选择线（位线）解码器508之间的形成检测电路510.成形检测电路510检测每个存储器的形成处理的完成通过测量第二选择线的电位波动或当通过第二选择线将用于形成处理的电压脉冲施加到要承载成形处理的多个存储单元时，流过第二选择线的电流量输出连接到相同的第一选择线（字线）的控制，以及用于防止电压施加到连接到完成形成处理的存储单元的第二选择线的控制。版权所有（C）2010，JPO＆INPIT

25. 发明专利

JP2010113742A Nonvolatile semiconductor memory device and control method of the same 有权
标题翻译：非易失性半导体存储器件及其控制方法
公开(公告)号：JP2010113742A
公开(公告)日：2010-05-20
申请号：JP2008283009
申请日：2008-11-04
申请人： Sharp Corp , シャープ株式会社
发明人： ISHIHARA KAZUYA , ISHIKAWA YUTAKA , OTA KEIJI
IPC分类号： G11C13/00 , G11C16/02
CPC分类号： G11C8/12 , G11C8/18 , G11C13/0007 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/0064 , G11C13/0069 , G11C2213/32 , G11C2216/22
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor storage device which achieves speedy rewrite operation to memory cells. SOLUTION: The device includes: a memory cell array including a first sub bank and a second sub bank obtained by arraying a plurality of nonvolatile memory cells in a matrix; a row decoder provided to the first sub bank and the second sub bank in common; a first column decoder and a second column decoder provided to the first sub bank and the second sub bank individually; and a control circuit which alternately carry out a first operation cycle which performs write operation to the first sub bank and reading operation for write verifying operation to the second sub bank and a second operation cycle which performs reading operation for write verifying operation to the first sub bank and writing operation to the second sub bank. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种实现对存储单元的快速重写操作的非易失性半导体存储装置。解决方案：该装置包括：存储单元阵列，包括通过以矩阵排列多个非易失性存储单元而获得的第一子库和第二子库; 行解码器，共同地提供给第一子库和第二子存储体; 第一列解码器和第二列解码器，分别提供给第一子存储体和第二子存储体; 以及控制电路，其交替地执行向第一子存储体执行写入操作的第一操作周期和对第二子存储体的写入验证操作的读取操作以及执行用于写入验证操作的读取操作的第二操作周期，银行和写作业务到第二个子银行。版权所有（C）2010，JPO＆INPIT

26. 发明专利

JP2006019444A Method for driving variable resistor element and storage device 有权
标题翻译：用于驱动可变电阻元件和存储器件的方法
公开(公告)号：JP2006019444A
公开(公告)日：2006-01-19
申请号：JP2004194799
申请日：2004-06-30
申请人： Sharp Corp , シャープ株式会社
发明人： HOSOI YASUNARI , TAMAI YUKIO , ISHIHARA KAZUYA , KOBAYASHI SHINJI , AWAYA NOBUYOSHI
IPC分类号： H01L27/105 , G11C13/00
CPC分类号： G11C29/50 , G11C13/0007 , G11C13/0069 , G11C29/50008 , G11C2013/009 , G11C2213/31
摘要： PROBLEM TO BE SOLVED: To provide a method of driving a variable resistor element including a perovskite oxide with electric resistance varying by applying voltage pulses, capable of stably keeping reversible resistance variation operations. SOLUTION: The variable resistor element is formed by providing the perovskite oxide 2 between a first electrode 1 and a second electrode 3. The element has resistance history characteristics that the electric resistance between the first electrode 1 and the second electrode 3 varies by applying voltage pulses with constant polarity between the first and second electrodes 1 and 3, and further the rate of change in the resistance value changes from positive to negative for an increase in accumulated pulse applied time during the application of the voltage pulses. The voltage pulses are applied to the variable resistor element so that the accumulated pulse applied time does not exceed the specific accumulated pulse applied time when the rate of change in the resistance value for the increase in the accumulated pulse applied time changes from positive to negative in the resistance history characteristics. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：解决的问题：提供一种驱动包括钙电位氧化物的可变电阻元件的方法，其中电阻通过施加电压脉冲而变化，能够稳定地保持可逆电阻变化操作。解决方案：可变电阻器元件通过在第一电极1和第二电极3之间提供钙钛矿氧化物2而形成。元件具有电阻历史特性，即第一电极1和第二电极3之间的电阻变化在第一和第二电极1和3之间施加具有恒定极性的电压脉冲，并且进一步地，在施加电压脉冲期间累积脉冲施加时间的增加，电阻值的变化率从正变化到负。电压脉冲被施加到可变电阻元件，使得当累积脉冲施加时间的增加的电阻值的变化率从正向变化到负时，累积脉冲施加时间不超过特定累积脉冲施加时间电阻历史特征。版权所有（C）2006，JPO＆NCIPI

27. 发明专利

JP2014199698A 半導体記憶装置及び半導体記憶装置の制御方法审中-公开
标题翻译：半导体存储器件和控制半导体存储器件的方法
公开(公告)号：JP2014199698A
公开(公告)日：2014-10-23
申请号：JP2013074622
申请日：2013-03-29
申请人：シャープ株式会社 , Sharp Corp , マイクロンメモリジャパン株式会社 , Micron Technology Japan Inc
发明人： NAGURA MITSURU , NAKANO TAKASHI , ISHIHARA KAZUYA , AWAYA NOBUYOSHI , KINO YUSUKE , HATTORI YASUKO
IPC分类号： G11C13/00
摘要：【課題】高速動作が可能な半導体記憶装置を提供する。【解決手段】半導体記憶装置1は、メモリセルアレイを複数に分割して成るブロックB1〜B4と、メモリセルが備える可変抵抗素子を低抵抗化させるセット動作と、メモリセルが備える可変抵抗素子を高抵抗化させるリセット動作と、をブロックB1〜B4毎に独立して実行する動作実行回路D1〜D4と、動作実行回路D1〜D4によるセット動作及びリセット動作の実行を制御する制御回路21と、を備える。制御回路21は、セット動作が実行されるブロック以外のブロックから、不要なデータを記憶しているメモリセルから成る不要データ領域を検出し、セット動作と並行して当該不要データ領域を成すメモリセルの少なくとも1つにリセット動作が実行されるように、動作実行回路D1〜D4を制御する。【選択図】図3
摘要翻译：要解决的问题：提供能够进行高速操作的半导体存储器件。解决方案：半导体存储器件1包括：通过将存储单元阵列分割成多个片而构成的块B1至B4; 对于每个块独立地执行用于降低包括在存储单元中的可变电阻元件的电阻的设置操作和用于增加包含在存储单元中的可变电阻元件的电阻的复位操作的操作执行电路D1至D4 B1至B4; 以及控制电路21，其控制由操作执行电路D1至D4执行设定操作和复位操作。控制电路21控制操作执行电路D1至D4，以检测由存储单元构成的不必要的数据区，该存储单元从执行设置操作的块以外的块存储不必要的数据，并且执行至少一个存储单元与所设置的操作并行地构成不必要的数据区域。

28. 发明专利

JP2013127826A Driving method of variable resistive element 审中-公开
标题翻译：可变电阻元件的驱动方法
公开(公告)号：JP2013127826A
公开(公告)日：2013-06-27
申请号：JP2011276358
申请日：2011-12-16
申请人： Sharp Corp , シャープ株式会社
发明人： TABUCHI YOSHIAKI , YAMAZAKI NOBUO , ONISHI JUNYA , TAMAI YUKIO , NAKANO TAKASHI , ISHIHARA KAZUYA , AWAYA NOBUYOSHI
IPC分类号： G11C13/00 , H01L27/105 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a driving method capable of reducing a load to be received by a variable resistive element at a reset operation.SOLUTION: In an operation for increasing the resistance (resetting) of a variable resistance element having a variable resistor structured of a metal oxide, a voltage applied across both electrodes of the variable resistive element is made to monotonously increase from the minimum voltage amplitude to the maximum voltage amplitude while taking a longer rising period than a predetermined minimum transition time, when applying a reset voltage pulse. Thereafter, the voltage applied across both electrodes of the variable resistive element is maintained to be at the maximum voltage amplitude during a predetermined maximum voltage applying period. Thereby, even if the maximum voltage amplitude is higher than a voltage required for the resetting voltage of the variable resistive element, a resetting operation starts in the middle of the rising period so that excessive spike current flowing in an early stage of a reset voltage application is suppressed.
摘要翻译：要解决的问题：提供一种能够减少在复位操作时由可变电阻元件接收的负载的驱动方法。解决方案：在用于增加具有由金属氧化物构成的可变电阻器的可变电阻元件的电阻（复位）的操作中，使可变电阻元件的两个电极上施加的电压从最小电压单调增加当施加复位电压脉冲时，以比预定的最小转变时间长的上升周期来振幅到最大电压幅度。此后，施加在可变电阻元件的两个电极上的电压在预定的最大电压施加周期期间保持在最大电压幅度。因此，即使最大电压幅度高于可变电阻元件的复位电压所需的电压，在上升周期的中间开始复位操作，使得在复位电压施加的早期流动的过量尖峰电流被压制版权所有（C）2013，JPO＆INPIT

29. 发明专利

JP2012221536A Semiconductor storage device 有权
标题翻译：半导体存储设备
公开(公告)号：JP2012221536A
公开(公告)日：2012-11-12
申请号：JP2011088400
申请日：2011-04-12
申请人： Sharp Corp , シャープ株式会社
发明人： NAGURA MITSURU , AWAYA NOBUYOSHI , ISHIHARA KAZUYA
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G06F11/1048 , G11C13/0007 , G11C29/52 , G11C2013/0073 , G11C2029/0411
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device which can efficiently perform detection of an error in data that may occur in performing continuous reading and correction of the erroneous data.SOLUTION: If an error in data is detected by an ECC circuit 106 when ECC encoded data is read in a semiconductor storage device 1 in which a variable resistive element using a metal oxide is used for storing information, bits where the error has been detected are corrected by applying, to all the memory cells where the error has been detected, a rewrite voltage pulse having a polarity reverse to that of an applied read voltage pulse on the assumption that an erroneous write, which is caused by application of a rewrite voltage pulse having the same polarity as that of the read voltage pulse, has occurred.
摘要翻译：解决的问题：提供一种半导体存储装置，其可以有效地执行在执行连续读取和校正错误数据时可能发生的数据中的错误的检测。解决方案：如果ECC编码数据在使用金属氧化物的可变电阻元件用于存储信息的半导体存储器件1中读取时，ECC电路106检测到数据中的错误，则错误的位通过将所检测到的误差的所有存储单元应用于具有与施加的读取电压脉冲的极性相反的极性的重写电压脉冲，通过将错误的写入（由应用已经发生具有与读取电压脉冲相同极性的电压脉冲。版权所有（C）2013，JPO＆INPIT

30. 发明专利

JP2012069221A Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：JP2012069221A
公开(公告)日：2012-04-05
申请号：JP2010214009
申请日：2010-09-24
申请人： Sharp Corp , シャープ株式会社
发明人： NAGURA MITSURU , ISHIHARA KAZUYA , YAMAZAKI NOBUO , KAWABATA MASARU
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C13/0028 , G11C13/0061 , G11C13/0064 , G11C13/0069 , G11C13/0097
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor memory including variable resistive elements which can stably and highly controllably perform writing under an intended electric resistance state in a writing operation by a random access.SOLUTION: Despite a resistive state of a variable resistive element of a memory cell to be rewritten (an erasing and writing operation), an erasing voltage pulse for making the resistive state of the variable resistive element a lowest erasure state is applied thereto. Later, a writing voltage pulse for making the resistive state of the variable resistive element an intended writing state is applied to a variable resistive element of the memory cell to be written. The writing voltage pulse is thus applied constantly after the application of the erasing voltage pulse, so as to avoid the continuous application of a plurality of writing voltage pulses. Furthermore, a memory cell array is configured of an even number of sub banks so as to apply the erasing voltage pulse to one sub bank and the writing voltage pulse to another sub bank alternately.
摘要翻译：要解决的问题：提供一种包括可变电阻元件的半导体存储器，其可以通过随机存取在写入操作中在期望的电阻状态下稳定且高度可控地执行写入。解决方案：尽管要重写的存储器单元的可变电阻元件的电阻状态（擦除和写入操作），但是为了使可变电阻元件的电阻状态为最低擦除状态的擦除电压脉冲被施加到其上。之后，将用于使可变电阻元件的电阻状态成为预定写入状态的写入电压脉冲施加到要写入的存储单元的可变电阻元件。在施加擦除电压脉冲之后，写入电压脉冲被不断地施加，以避免连续施加多个写入电压脉冲。此外，存储单元阵列由偶数个子库构成，以将擦除电压脉冲施加到一个子存储体，并将写入电压脉冲交替地施加到另一个子存储体。版权所有（C）2012，JPO＆INPIT

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