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1. 发明专利

JP2012064286A Nonvolatile semiconductor storage device and method for controlling nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件及控制非易失性半导体存储器件的方法
公开(公告)号：JP2012064286A
公开(公告)日：2012-03-29
申请号：JP2010209650
申请日：2010-09-17
申请人： Sharp Corp , シャープ株式会社
发明人： KAWABATA MASARU , YAMAZAKI NOBUO
IPC分类号： G11C13/00
摘要： PROBLEM TO BE SOLVED: To effectively prevent a deterioration in a variable resistive element of an RRAM by suppressing variations of resistive states.SOLUTION: A memory cell array 10 provided with a plurality of memory cells M provided with a variable resistive element R whose electric resistance changes to two or more different resistive states, a determination circuit for partitioning the range of resistance values, which the variable resistive element R can take, into a plurality of target ranges and a plurality of middle ranges and determining whether the resistance value of the memory cell M is within any range among the plurality of target ranges and the plurality of middle ranges, and a write circuit 13 for applying a voltage pulse to the variable resistive element R so as to make a resistance value be within one range among the target ranges and writing information in the memory cells M are provided. Two or more middle ranges exist between two adjacent target ranges. In the determination circuit, a voltage pulse is applied to a memory cell M in which the resistance value of the memory cell M is not determined to be within a predetermined target range on a first application condition set differently at least in each middle range.
摘要翻译：要解决的问题：通过抑制电阻状态的变化来有效地防止RRAM的可变电阻元件的劣化。解决方案：提供有多个存储单元M的存储单元阵列10，存储单元M设置有电阻变化到两个或更多个不同电阻状态的可变电阻元件R，用于分隔电阻值的范围的确定电路，可变电阻元件R可以取入多个目标范围和多个中间范围，并且确定存储单元M的电阻值是否在多个目标范围和多个中间范围内的任何范围内，并且写入提供用于向可变电阻元件R施加电压脉冲以使得电阻值在目标范围内的一个范围内并且在存储单元M中写入信息的电路13。在两个相邻目标范围之间存在两个或多个中间范围。在确定电路中，在至少在每个中间范围内不同地设置的第一应用条件下，将电压脉冲施加到存储单元M，其中存储单元M的电阻值未被确定在预定目标范围内。版权所有（C）2012，JPO＆INPIT

2. 发明专利

JP2012038408A Semiconductor storage device and its driving method 有权
标题翻译：半导体存储器件及其驱动方法
公开(公告)号：JP2012038408A
公开(公告)日：2012-02-23
申请号：JP2011078419
申请日：2011-03-31
申请人： Sharp Corp , シャープ株式会社
发明人： YAMAZAKI NOBUO , OTA YOSHIJI , ISHIHARA KAZUYA , NAGURA MITSURU , KAWABATA MASARU , AWAYA NOBUYOSHI
IPC分类号： G11C13/00
CPC分类号： G11C13/0007 , G11C7/1048 , G11C7/12 , G11C13/0004 , G11C13/0026 , G11C13/0038 , G11C13/0069 , G11C2013/0071 , G11C2213/79 , G11C2213/82
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor storage device capable of high-speed operation by solving the problem in which a short-time voltage pulse cannot be applied to a storage element from a common line side.SOLUTION: A semiconductor storage device 1 comprises a memory cell array 100 in which a plurality of memory cells including two-terminal storage elements and selection transistors connected in series are arranged in matrix, a first voltage application circuit 101 for applying a rewriting voltage pulse to a first bit line, and a second voltage application circuit 102 for applying a pre-charge voltage to a bit line and a common line. The memory cell is rewritten in a manner that, after both ends of the memory cell are pre-charged in advance by the second voltage application circuit 102 at the same voltage, the first voltage application circuit 101 applies via the bit line the rewriting voltage pulse to one end of the memory cell to be rewritten. During the application of the rewriting voltage pulse, the second voltage application circuit 102 keeps applying the pre-charge voltage to the other end of the memory cell via the common line CML.
摘要翻译：要解决的问题：提供一种能够通过解决从公共线路侧不能将短时电压脉冲施加到存储元件的问题来提供能够进行高速操作的半导体存储装置。解决方案：半导体存储装置1包括：存储单元阵列100，其中包括串联连接的两端存储元件和选择晶体管的多个存储单元排列成矩阵;第一电压施加电路101，用于施加重写电压脉冲到第一位线，以及第二电压施加电路102，用于将预充电电压施加到位线和公共线。以这样的方式重写存储器单元，即在相同电压下由第二电压施加电路102预先对存储单元的两端进行预充电之后，第一电压施加电路101经由位线施加重写电压脉冲到要重写的存储器单元的一端。在施加重写电压脉冲期间，第二电压施加电路102经由公共线CML继续将预充电电压施加到存储单元的另一端。版权所有（C）2012，JPO＆INPIT

3. 发明专利

JP2012033649A Nonvolatile semiconductor storage device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012033649A
公开(公告)日：2012-02-16
申请号：JP2010171079
申请日：2010-07-29
申请人： Sharp Corp , シャープ株式会社
发明人： ONISHI JUNYA , YAMAZAKI NOBUO , ISHIHARA KAZUYA , INOUE YUSHI , TAMAI YUKIO , AWAYA NOBUYOSHI
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L45/04 , H01L27/2436 , H01L45/1233 , H01L45/146
摘要： PROBLEM TO BE SOLVED: To provide a variable resistive element which can stably perform switching operation owing to reduction in characteristic variation by inhibiting steep current associated with completion of forming processing and to provide a nonvolatile semiconductor storage device provided with the variable resistive element.SOLUTION: The nonvolatile semiconductor storage device uses a variable resistive element 2 sandwiching a resistance change layer 13 between a first electrode 12a and a second electrode 14 for storing information. The variable resistive element 2 includes a buffer layer 12b inserted between the first electrode 12a and the resistance change layer 13 at which a switching boundary surface is formed. The buffer layer 12b and the resistance change layer 13 both include n-type metal oxide. Materials of the buffer layer 12a and the resistance change layer 13 are selected such that energy of conduction band minimum of the n-type metal oxide included in the buffer layer 12b is lower than that of the n-type metal oxide included in the resistance change layer 13.
摘要翻译：要解决的问题：提供一种可变电阻元件，其可以通过抑制与形成处理完成相关的陡峭电流而由于特性变化的降低而稳定地执行开关操作，并且提供设置有可变电阻元件的非易失性半导体存储器件。解决方案：非易失性半导体存储装置使用在第一电极12a和第二电极14之间夹着电阻变化层13的可变电阻元件2用于存储信息。可变电阻元件2包括插入在第一电极12a和形成开关边界面的电阻变化层13之间的缓冲层12b。缓冲层12b和电阻变化层13都包括n型金属氧化物。选择缓冲层12a和电阻变化层13的材料，使得包括在缓冲层12b中的n型金属氧化物的最小导电能量比包含在电阻变化中的n型金属氧化物的能量低第13层。版权所有（C）2012，JPO＆INPIT

4. 发明专利

JP2010009662A Nonvolatile semiconductor memory device and driving method therefor 有权
标题翻译：非易失性半导体存储器件及其驱动方法
公开(公告)号：JP2010009662A
公开(公告)日：2010-01-14
申请号：JP2008166406
申请日：2008-06-25
申请人： Sharp Corp , シャープ株式会社
发明人： YAMAZAKI NOBUO , AWAYA NOBUYOSHI , ISHIHARA KAZUYA , TABUCHI YOSHIAKI
IPC分类号： G11C13/00 , H01L27/10 , H01L45/00 , H01L49/00
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which ensures stable rewrite operation by changing a resistance state for sure without enlarging a memory cell area and chip area. SOLUTION: In a variable resistance element 1, the resistance is reduced by applying voltage so that a current whose absolute value is Is or more flows from a terminal 1a to a terminal 1b, and the resistance is increased by applying voltage so that a current whose absolute value is Ir or more flows from a terminal 1b to a terminal 1a. When Ir COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供一种非易失性半导体存储器件，其通过改变电阻状态来确保稳定的重写操作，而不增大存储单元面积和芯片面积。解决方案：在可变电阻元件1中，通过施加电压来降低电阻，使得绝缘值为Is以上的电流从端子1a流到端子1b，并且通过施加电压来增加电阻，使得绝缘值为Ir或更大的电流从端子1b流到端子1a。当Ir

5. 发明专利

JP2013251017A Semiconductor storage device and driving method of memory cell array 审中-公开
标题翻译：存储器阵列的半导体存储器件和驱动方法
公开(公告)号：JP2013251017A
公开(公告)日：2013-12-12
申请号：JP2012122946
申请日：2012-05-30
申请人： Sharp Corp , シャープ株式会社
发明人： NAGURA MITSURU , KAWABATA MASARU , YAMAZAKI NOBUO
IPC分类号： G11C13/00 , H01L45/00 , H01L49/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0071 , G11C2013/0083 , G11C2213/77 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a highly reliable semiconductor storage device capable of operating stably, and a driving method of the same.SOLUTION: A semiconductor storage device comprises a variable resistive element. When an initialization operation is performed for alternately and plural times performing setting (reducing resistance) and resetting (increasing resistance)of the variable resistive element, a plurality of memory cells are selected by selecting one or a plurality of word lines and a bit line group including a plurality of bit lines, and pulses of a set voltage Vand a reset voltage Vare alternately applied plural times from the bit line side to each of the plurality of memory cells with a constant voltage Vbeing applied to a selected source line.
摘要翻译：要解决的问题：提供能够稳定运行的高度可靠的半导体存储装置及其驱动方法。解决方案：半导体存储装置包括可变电阻元件。当进行可变电阻元件的设定（降低电阻）和复位（增加电阻）的交替和多次的初始化操作时，通过选择一个或多个字线和位线组来选择多个存储单元包括多个位线，并且以施加到所选择的源极线的恒定电压Vbeing，从位线侧向每个多个存储单元交替地施加复位电压Vare的多个位置的脉冲和复位电压Vare多次。

6. 发明专利

JP2013239223A Nonvolatile semiconductor memory device and method of driving memory cell array 审中-公开
标题翻译：非易失性半导体存储器件和驱动存储器单元阵列的方法
公开(公告)号：JP2013239223A
公开(公告)日：2013-11-28
申请号：JP2012111942
申请日：2012-05-15
申请人： Sharp Corp , シャープ株式会社
发明人： KAWABATA MASARU , NAGURA MITSURU , YAMAZAKI NOBUO
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0002 , G11C2013/0083
摘要： PROBLEM TO BE SOLVED: To provide a reliable nonvolatile semiconductor memory device capable of a stable operation, and a driving method thereof.SOLUTION: In performing an initialization operation, in which the set (lowering resistance) and reset (increasing resistance) of a variable resistive element are alternately performed a plurality of times, in a nonvolatile semiconductor memory device including the variable resistive element, one or a plurality of each of a first bit line and second bit line are selected out of a bit line group that consists of a plurality of bit lines, and a voltage application operation in which a first voltage VA is applied to the first bit line(s) and a second voltage VB is applied to the second bit line(s) is performed a plurality of times while a source line is set in a floating state. In this case, the first bit line and second bit line for individual voltage application operations are selected so as to have all the bit lines of the bit line group selected as the first bit line and the second bit line once through the plurality times of voltage application.
摘要翻译：要解决的问题：提供一种能够稳定工作的可靠的非易失性半导体存储器件及其驱动方法。解决方案：在执行初始化操作中，其中设定（降低电阻）和复位（增加电阻）变量电阻元件在包括可变电阻元件的非易失性半导体存储器件中交替执行多次，在由多个元件组成的位线组中选择第一位线和第二位线中的一个或多个并且将第一电压VA施加到第一位线并且将第二电压VB施加到第二位线的电压施加操作多次执行，而源极线被设置为浮动状态。在这种情况下，选择用于各个电压施加操作的第一位线和第二位线，使得位线组的所有位线被选择为第一位线，而第二位线通过多次电压应用。

7. 发明专利

JP2012079367A Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：JP2012079367A
公开(公告)日：2012-04-19
申请号：JP2010221877
申请日：2010-09-30
申请人： Sharp Corp , シャープ株式会社
发明人： KAWABATA MASARU , YAMAZAKI NOBUO , ISHIHARA KAZUYA , ONISHI JUNYA , AWAYA NOBUYOSHI , TAMAI YUKIO
IPC分类号： G11C13/00 , H01L27/105 , H01L45/00 , H01L49/00
CPC分类号： G11C11/5685 , G11C13/0007 , G11C2013/0071 , G11C2013/0073 , G11C2013/0083 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device that has superior data retention characteristics at a high temperature of approximately 260°C.SOLUTION: The nonvolatile semiconductor memory device includes a memory cell array for storing user data which is constituted by arraying a plurality of memory cells each equipped with a variable resistance element. The variable resistance element includes a first electrode 2, a second electrode 3, and a variable resistor 4 interposed between both the electrodes and made of metal oxide such that the first electrode 2 is formed of a conductive material forming an ohmic junction with the variable resistor 4 and the second electrode 3 is formed of a conductive material forming a non-ohmic junction with the variable resistor 4, and changes in resistance state between two or more different low-resistance states as a voltage is applied between both the electrodes to stay nonvolatile in the resistance state after the change in the resistance state. In a state before the memory cell array is used for storing the user data, variable resistance elements of all the memory cells in the memory cell array are made high in resistance into a resistance state of the highest resistance between the two or more different resistance states.
摘要翻译：要解决的问题：提供一种在约260℃的高温下具有优异的数据保存特性的非易失性半导体存储器件。解决方案：非易失性半导体存储器件包括用于存储用户数据的存储单元阵列，该存储单元阵列通过排列各自配备有可变电阻元件的多个存储单元构成。可变电阻元件包括插入在两个电极之间并由金属氧化物制成的第一电极2，第二电极3和可变电阻器4，使得第一电极2由与可变电阻器形成欧姆结的导电材料形成 4并且第二电极3由形成与可变电阻器4的非欧姆结的导电材料形成，并且在两个电极之间施加作为电压的两个或更多个不同的低电阻状态之间的电阻状态的变化以保持非易失性在电阻状态改变后的电阻状态。在存储单元阵列用于存储用户数据之前的状态下，使存储单元阵列中的所有存储单元的可变电阻元件的电阻变得高于两个或更多个不同电阻状态之间的最高电阻的电阻状态。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2008147343A Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：JP2008147343A
公开(公告)日：2008-06-26
申请号：JP2006331689
申请日：2006-12-08
申请人： Sharp Corp , シャープ株式会社
发明人： YAMAZAKI NOBUO , HOSOI YASUNARI , AWAYA NOBUYOSHI , SATO SHINICHI , TANAKA KENICHI
IPC分类号： H01L27/10 , G11C13/00 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , G11C13/0007 , G11C13/003 , G11C2213/15 , G11C2213/32 , G11C2213/34 , G11C2213/71 , G11C2213/72 , G11C2213/76 , G11C2213/77 , G11C2213/79 , H01L27/2409 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633
摘要： PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory which can perform each stable high-speed switching operation to its each variable-resistance element by applying thereto each voltage having either positive or negative polarity, without interposing any difference between the long and short applying times of each voltage. SOLUTION: The nonvolatile semiconductor memory 10 has each variable-resistance element of a two-terminal structure wherein by applying to both its ends each voltage of satisfying predetermined conditions, its resistance property specified by the voltage-current property of both its ends can transit between the stably obtainable two resistance-property states comprising high and low resistances, that is, each variable-resistance element of a two-terminal structure has such a property that when applying to it the first-polarity voltage having an absolute value not lower than a first threshold, it transits from a low-resistance state to a high-resistance state, and when applying to it the second-polarity voltage having an absolute value not lower than a second threshold, it transits from the high-resistance state to the low-resistance state. Further, the nonvolatile semiconductor memory has each load circuit, whose load resistance is adjustable, connected in series with each variable-resistance element and has each voltage generating circuit capable of applying a voltage to both the ends of each series circuit. Moreover, the nonvolatile semiconductor memory is so constituted that the transition between the states of each variable-resistance element is made possible by adjusting the resistance of each load circuit. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供一种非易失性半导体存储器，其可以通过向每个可变电阻元件施加具有正极性或负极性的每个电压来执行每个稳定的高速开关操作，而不会在长的并且每个电压的施加时间短。解决方案：非易失性半导体存储器10具有两端结构的每个可变电阻元件，其中通过向其两端施加满足预定条件的每个电压，其两端的电压 - 电流特性指定的电阻特性可以在包括高电阻和低电阻的稳定可获得的两个电阻特性状态之间转换，即，两端结构的每个可变电阻元件具有如下特性：当向其施加绝对值不是的第一极性电压时低于第一阈值时，它从低电阻状态转变到高电阻状态，并且当施加具有不低于第二阈值的绝对值的第二极性电压时，其从高电阻状态到低电阻状态。此外，非易失性半导体存储器具有负载电阻可调的每个负载电路与每个可变电阻元件串联连接，并且具有能够向每个串联电路的两端施加电压的每个电压产生电路。此外，非易失性半导体存储器的结构使得通过调节每个负载电路的电阻使得每个可变电阻元件的状态之间的转变成为可能。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007134603A Method for manufacturing nonvolatile semiconductor memory device comprising variable resistive element 有权
标题翻译：制造包含可变电阻元件的非易失性半导体存储器件的方法
公开(公告)号：JP2007134603A
公开(公告)日：2007-05-31
申请号：JP2005327982
申请日：2005-11-11
申请人： Sharp Corp , シャープ株式会社
发明人： YAMAZAKI NOBUO
IPC分类号： H01L27/10 , H01L45/00 , H01L49/00
CPC分类号： H01L27/101 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing a nonvolatile semiconductor memory device capable of suppressing variations in resistance value according to the difference of a PCMO crystallinity of a variable resistive element and completely securing a circuit operational margin.
SOLUTION: The method for manufacturing the semiconductor memory device with the variable resistive element for storing data formed between an upper electrode and a lower electrode comprises the steps of sputtering an electrically conductive metallic oxide in an atmosphere including no oxygen, and forming the variable resistive element.
COPYRIGHT: (C)2007,JPO&INPIT

10. 发明专利

JP2014102866A Semiconductor device and method of controlling semiconductor device 审中-公开
标题翻译：半导体器件和控制半导体器件的方法
公开(公告)号：JP2014102866A
公开(公告)日：2014-06-05
申请号：JP2012254595
申请日：2012-11-20
申请人： Micron Technology Japan Inc , マイクロンメモリジャパン株式会社 , Sharp Corp , シャープ株式会社
发明人： MAE KENJI , NAGURA MITSURU , ISHIHARA KAZUYA , YAMAZAKI NOBUO
IPC分类号： G11C13/00
CPC分类号： G11C13/0069 , G11C13/0028 , G11C13/0064 , G11C13/0097 , G11C2213/79
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device using a variable resistive element that does not pass current more than required and completes a write operation in an appropriate number of times.SOLUTION: A semiconductor device includes: a variable resistive element and a control circuit that controls the resistance state of the variable resistive element by controlling current between one end and the other end of the variable resistive element. The control circuit causes a first current to flow from the one end of the variable resistive element to the other end so as to change the variable resistive element from a first resistance state to a second resistance state. In addition, the control circuit causes a third current to flow from the other end to the one end after causing a second current smaller than the first current to flow from the one end to the other end of the variable resistive element, so as to change the variable resistive element from the second resistance state to the first resistance state.
摘要翻译：要解决的问题：提供一种使用不超过所需电流的可变电阻元件的半导体器件，并以适当次数完成写入操作。解决方案：半导体器件包括：可变电阻元件和控制电路其通过控制可变电阻元件的一端和另一端之间的电流来控制可变电阻元件的电阻状态。控制电路使第一电流从可变电阻元件的一端流到另一端，以便将可变电阻元件从第一电阻状态改变到第二电阻状态。此外，控制电路使得第三电流在使得小于第一电流的第二电流从可变电阻元件的一端流到另一端之后从另一端流向一端，以便改变从第二电阻状态到第一电阻状态的可变电阻元件。

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