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21. 发明专利

JPS5620356A BACKUP SYSTEM OF SIGNAL TRANSMISSION SYSTEM 失效
公开(公告)号：JPS5620356A
公开(公告)日：1981-02-25
申请号：JP9496179
申请日：1979-07-27
申请人： HITACHI LTD
发明人： MATSUO SATOSHI , MURAI KATSUJI , KODAMA YUKINORI
IPC分类号： H04B1/74 , H04L12/437
摘要： PURPOSE:To back a transmission line, etc., up adequately with regard to its abnormality by doubling a signal transmission system and then by providing a loop controller with functions of power-down bypassing, subcontroller bypassing, loop breaking and channel switching. CONSTITUTION:Master controller 1 is provided at a main system side and through transmission line 2, signal transmission and reception to and from loop controllers 42-45 following loop controller 41 are carried out. Those loop controllers 41-45 are arranged corresponding to subcontrollers 31-35 and a closed loop is constituted which starts with controller 1 and returns to controller 1 by circulating through loop controllers 41-45 in series. This transmission line 2 consists of systems A and B by doubling and the section between controller 1 and buffer amplifiers 51 and 52 is also doubled. Then, loop controllers 41-45 are provided with functions of power-down bypassing, subcontroller bypassing, loop breaking and channel switching so as to treat properly abnormality such as an electric power failure and controller trouble.

22. 发明专利

JPH0159639B2 失效
公开(公告)号：JPH0159639B2
公开(公告)日：1989-12-19
申请号：JP16807380
申请日：1980-12-01
申请人： HITACHI LTD
发明人： MATSUO SATOSHI , MURAI KATSUJI
IPC分类号： G08C25/00 , G08C13/00 , G08C15/06 , G08C19/00 , G08C19/28

23. 发明专利

JPS5743202A Feed forward control system 失效
标题翻译：进给前进控制系统
公开(公告)号：JPS5743202A
公开(公告)日：1982-03-11
申请号：JP11704980
申请日：1980-08-27
申请人： Hitachi Ltd , Japan Atom Energy Res Inst
发明人： OGATA ATSUSHI , MATSUO SATOSHI , MURAI KATSUJI , KODAMA YUKINORI
IPC分类号： G05B11/32 , G05B5/01
CPC分类号： G05B5/01
摘要： PURPOSE:To compensate and control variation caused by an uncertain causes, by fetching an accmpanied phenomonon with an incidental abnormal phenomenon in real time, obtaining the delay time and compensating amount based on the correlation with the deviation of status amount of said data and the abnormal phenomenon, and giving correction. CONSTITUTION:The state amount of an accompanied phenomenon 6 appeared ahead an abnormal phenomenon is fetched with a detector 7, and based on the correlation with the deviation of state amount caused to the control variable due to abnormal phenomenon, the amount to be compensated via a compensation amount and delay time operation block 8, and the delay time for the compensation control in coincidence with the time delay until an abnormal phenomenon is actually appeared from the production of uncertain causes, can be obtained. The result is realized by a delay circuit 9, summing point 10 and controller 2, the status amount deviation due to abnormal phenomenon is cancelled for the output of the controller to keep the balancing of the control variable.
摘要翻译：目的：为了补偿和控制由不确定因素引起的变化，通过实时发现附带异常现象，获得延迟时间和补偿量，根据与所述数据的状态量的偏差的相关性和异常现象，给予纠正。构成：伴随现象6的状态量出现在检测器7之前的异常现象之前，并且基于由于异常现象引起的与控制变量的状态量的偏差的相关性，通过a 补偿量和延迟时间操作块8，并且可以获得与不确定原因的产生实际出现异常现象的时间延迟一致的补偿控制的延迟时间。结果由延迟电路9，求和点10和控制器2实现，由于异常现象引起的状态量偏差被取消，控制器的输出保持控制变量的平衡。

24. 发明专利

JPS5654503A FEED FORWARD CONTROLLER 失效
公开(公告)号：JPS5654503A
公开(公告)日：1981-05-14
申请号：JP13077979
申请日：1979-10-12
申请人： JAPAN ATOMIC ENERGY RES INST , HITACHI LTD
发明人： OGATA ATSUSHI , NINOMIYA HIROMASA , MATSUO SATOSHI , MURAI KATSUJI , KAMIYAMA YASUO
IPC分类号： G21B1/11 , G05B11/32 , G05B11/36 , G21B1/00 , G21B1/25
摘要： PURPOSE:To exercise highly precise control even in occurrence of a disturbance, by exercising control over a system while forecasting fluctuations of the system. CONSTITUTION:A nuclear-fusion experimental device is unable to cope with complicate motion of plasma only in programmed process. This complicate motion acts upon the process as a disturbance. Condition judgement part 5 receives a coil voltage and electric current from coil 3 and fetches signals of a plasma current, density, position, shape, etc., from plasma 4. On the basis of those input signal, whether the motion can be regarded as a disturbance is judged and according to the result, the fluctuation extent is forecasted on the basis of various fluctuation data due to the right previous disturbance to exercise control. For this purpose, the frequency and voltage of the AC electric power source are not controlled directly and the output of thyristor phase controller 14 influenced by them is controlled right previously.

25. 发明专利

JPS6085370A ANALOG DATA RECORDER 失效
公开(公告)号：JPS6085370A
公开(公告)日：1985-05-14
申请号：JP19233983
申请日：1983-10-17
申请人： JAPAN ATOMIC ENERGY RES INST , HITACHI LTD
发明人： KONDOU IKUROU , YOSHINO TAKAHARU , MATSUO SATOSHI , MURAI KATSUJI , KODAMA YUKINORI
IPC分类号： G01R19/25
摘要： PURPOSE:To fetch and store an analog data efficiently by performing a simultaneous sample holding in the analog input while data is stored orderly for each channel in the storing of the data. CONSTITUTION:An S-H circuit 101 holds analog signals for a fixed time in all channels all at once simultaneously with the reception of a sample holding command 3, while a holding signal A is converted into a digitized signal C over all channels one channel at a time with an analog multiplexer circuit 101B and an analog-digital conversion circuit 101C whereby multichannel analog signals can be sampled simultaneously at the same time. In addition, a memory storage control circuit 101E is inserted to specify the storage address of a data memory according to the channel and the sampling time to allow the storing of data in the train unit as translated from those in the channel unit.

26. 发明专利

JPS5743268A Preprogram controlling system 失效
标题翻译： PREPROGRAM控制系统
公开(公告)号：JPS5743268A
公开(公告)日：1982-03-11
申请号：JP11705180
申请日：1980-08-27
申请人： Hitachi Ltd , Japan Atom Energy Res Inst
发明人： OGATA ATSUSHI , SUZUKI YASUO , MATSUO SATOSHI , MURAI KATSUJI , KAMIYAMA YASUO
IPC分类号： G05B17/00 , G05B19/02 , G06F17/50 , G21B1/11 , G21B1/25
CPC分类号： G06F17/5009
摘要： PURPOSE:To highly accurately perform system control based on optional patterns, by obtaining in advance controlling amounts against optional target values of the system in the form of time series and by giving this controlling amount as an input at every constant sampling period. CONSTITUTION:When an operator sets a desired system target value 100, at a program 11 for preparing preprograms, linear approximations regarding input/ output are performed for every continuous controlling section on controlling amounts to be inputted first into a simulation model, and an input value 101 is roughly obtained from the gradient to the target value. This rough value is inputted into the simulation model 13, and a controlling amount which minimizes the evaluation function regarding the difference between its output response 102 and the target value, is repeatedly obtained. The controlling amount thus obtained is used as a preprogram controlling amount 103 and a real system 14 is operated. Then real output data 104 of the real system 14 is fetched and the difference between the real output data 104 and the simulation output obtained when the preprogram is prepared, is obtained, and then, model modifications are performed by a program for modification 12.
摘要翻译：目的：为了高精度地执行基于可选模式的系统控制，可以通过以时间序列的形式提前控制量与系统的可选目标值，并在每个恒定的采样周期内将该控制量作为输入。构成：当操作者设定期望的系统目标值100时，在用于准备前程序的程序11中，对于每个连续控制部分，对要首先输入到模拟模型的控制量执行关于输入/输出的线性近似，并且输入值 101大致从梯度到目标值获得。该粗略值被输入到模拟模型13中，并且重复地获得使其关于其输出响应102和目标值之间的差异的评估函数最小化的控制量。将这样获得的控制量用作预编程控制量103，并且操作实际系统14。然后，获取实际系统14的实际输出数据104，并且获得实际输出数据104与准备预编程时获得的模拟输出之间的差异，然后由修改程序12执行模型修改。

27. 发明专利

JPS5731045A Digital integrator for bipolar signal 失效
标题翻译：双极信号数字积分器
公开(公告)号：JPS5731045A
公开(公告)日：1982-02-19
申请号：JP10502980
申请日：1980-08-01
申请人： Hitachi Ltd
发明人： NAKAYAMA HISAHIDE , MATSUO SATOSHI
IPC分类号： G06F7/64 , G06F7/60
CPC分类号： G06F7/60
摘要： PURPOSE:To execute a digital integration satisfactorily, by adding constant offset voltage to an input voltage signal which is varied extending over positive and negative ranges, outputting it as a signal which is varied in only the positive range, converting it to a frequency signal, counting it, and subtracting and correcting the offset voltage portion. CONSTITUTION:An input signal from a preamplifier 100 is sent to an addeer 210 of a bipolar digital integrator 200, and a constant offset voltage signal is added. This voltage signal is outputted as a signal which is varied in only the positive range, is converted to frequency by a frequency converter 220, and is counted by a counter 230. Its output is inputted to a control computer system 300, and from the system 300 to the integrator 200 are provided control signals such as integration start, integration stop, initial value setting, etc. In this way, even when an input level of a bipolar analog input signal is near zero, a digital integration is executed without losing a follow-up property to an input variation.
摘要翻译：目的：为了令人满意地执行数字积分，通过向正范围和负范围内延伸的输入电压信号增加恒定偏移电压，将其输出为仅在正范围内变化的信号，将其转换为频率信号，对其进行计数，以及减去和校正偏移电压部分。构成：将来自前置放大器100的输入信号发送到双极型数字积分器200的加法器210，并且增加恒定的偏移电压信号。该电压信号作为仅在正的范围变化的信号输出，由频率转换器220转换为频率，并由计数器230进行计数。其输出被输入到控制计算机系统300，并且从系统 300向积分器200提供诸如积分开始，积分停止，初始值设定等的控制信号。以这种方式，即使当双极模拟输入信号的输入电平接近零时，执行数字积分而不丢失对输入变体的后续属性。

28. 发明专利

JPS5731044A Multipurpose digital integral device 失效
标题翻译：多媒体数字整合设备
公开(公告)号：JPS5731044A
公开(公告)日：1982-02-19
申请号：JP10502880
申请日：1980-08-01
申请人： Hitachi Ltd
发明人： MATSUO SATOSHI , MURAI KATSUJI , NAKAYAMA HISAHIDE
IPC分类号： H03M1/12 , G06F3/05 , G06F7/64 , H03M1/58
CPC分类号： H03M1/58
摘要： PURPOSE:To raise resolution and also to eliminate variation of resolution and response speed, by converting an analog signal of a measuring result to a digital signal, integrating this output further, and using it as a digital integrator or an A/D converter. CONSTITUTION:An analog signal of a measuring result is converted to a digital signal by an A/D converter 2, and its output is inputted to an adder 3 and is added in order. This added value is transferred to a latching register 4 by a period which is obtained by frequency-dividing 6 an external clock signal 11, and in this way, a value which has been inputted to the register 4 is updated to a new value whenever the next latching signal comes in. An A/D conversion period is set optionally by the frequency being below an external clock signal, by a dividing factor setting signal 12 using a dividing factor of frequency dividers 6, 6'. When using only as an A/D converter, a changeover switch 13 is set to a time delaying circuit 7 so that the A/D conversion period which is obtained by the frequency divider 6 becomes equal to the latching period which is obtained by the frequency divider 6'.
摘要翻译：目的：为了提高分辨率并消除分辨率和响应速度的变化，通过将测量结果的模拟信号转换为数字信号，进一步集成该输出，并将其用作数字积分器或A / D转换器。构成：通过A / D转换器2将测量结果的模拟信号转换为数字信号，并将其输出输入到加法器3，并依次添加。该附加值通过对外部时钟信号11进行6分频而获得的周期被传送到锁存寄存器4，并且以这种方式，只要输入到寄存器4的值被更新为新值，下一个锁存信号进入。通过使用分频器6,6'的分频因子的分频因子设置信号12，可选择地通过频率低于外部时钟信号的A / D转换周期来设置A / D转换周期。当仅用作A / D转换器时，将转换开关13设置到时间延迟电路7，使得由分频器6获得的A / D转换周期等于由频率获得的锁存周期分隔线6'。

29. 发明专利

JPS56119858A HIGHHSPEED COLLECTING PROCESSOR FOR ANALOG DATA 失效
公开(公告)号：JPS56119858A
公开(公告)日：1981-09-19
申请号：JP2272280
申请日：1980-02-27
申请人： HITACHI LTD
发明人： MATSUO SATOSHI , MURAI KATSUJI
IPC分类号： G01R19/25 , G01D3/02 , H03M1/18
摘要： PURPOSE:To fetch data by a minimum amount, at a high S/N ratio and with high precision, by switching amplifier gains corresponding to the amplitude of the analog signal and by switching sampling periods corresponding to variation value of signal. CONSTITUTION:Signals from detectors D1 and D2 are supplied to variable gain amplifiers 2 and 13, which are always controlled to the most suitable gains by level detectors 5 and 15 and gain controllers 6 and 16, via low-pass filters 1 and 12. Further, outputs of amplifier are stored in common-use data memory 4 via A/D converters 3 and 14 supplied with sampling pulses from clock generators 9 and 19 controlled according to variation rates detected by variation detectors 7 and 17. On the other hand, gain and sampling frequencies of the amplifiers controlled in real time during measurement are recorded by gain timing recorder 8 and clock generator 9. Consequently, a wide-band and wide dynamic-range analog signal can be collected with the best gain and at the best period.

30. 发明专利

JPS5687123A VARIABLE CLOCK TIMING SYSTEM 失效
公开(公告)号：JPS5687123A
公开(公告)日：1981-07-15
申请号：JP16412079
申请日：1979-12-19
申请人： HITACHI LTD
发明人： MATSUO SATOSHI , MURAI KATSUJI
IPC分类号： G06F1/08 , G06F1/04
摘要： PURPOSE:To give a timing command with the required accuracy of time and in accordance with the required time control band, by generating the division factor of an optional value in the real time variably against the basic frequency of the clock signal. CONSTITUTION:The coded control signal S(n) and the preset signal PS are delivered from the control device 30 in order to designate the division factor (n) and to set the time band for time control of the control subject 32 to the timer groups TM1-TMm respectively. Thus the control times T1, T2 and T3 are set to the timers TM1, TM2 and TM3 each by the signal PS. Then the clock signal C(f) the frequency of which is varied based on the signal S(n) delivered from the device 30 is taken in with the control time set to the timers TM1, TM2 and TM3 each, and the timing command based on the signal C(f) is given to the control subject 32. In such way, a timing command can be given with the time accuracy that is required in accordance with the required time control band.

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