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21. 发明专利

JPH02166559A ANALYZING METHOD FOR DATA BASE OPERATION LANGUAGE 失效
公开(公告)号：JPH02166559A
公开(公告)日：1990-06-27
申请号：JP32066388
申请日：1988-12-21
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOGI KEIJI , YAMAMOTO YOICHI , NAMIOKA MIYOKO , SATO KAZUHIRO
IPC分类号： G06F12/00 , G06F17/30
摘要： PURPOSE:To reduce the user load for production of an application program by acquiring the information on the parameter necessary for execution of a dynamic data base operation when the analysis is requested. CONSTITUTION:An application program 20 delivers the information on the parameter necessary for execution of a data base operation language to the receiver side together with a data base operation language sentence when a dynamic analysis request is received for the language sentence. A data base control system 10 analyzes the received language sentence and sends the data type of a variable parameter, the field name of the record to be retrieved, and the data type back to the designated receiver side. Thus the program 20 can set the parameter information based on the information on the parameter after the analysis and therefore is not required to analyze the data base operation language sentence by itself.

22. 发明专利

JPS63292321A RECORD RETRIEVAL PROCESSING SYSTEM 失效
公开(公告)号：JPS63292321A
公开(公告)日：1988-11-29
申请号：JP12953487
申请日：1987-05-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOGI KEIJI , MUTO HIDEO
IPC分类号： G06F17/30
摘要： PURPOSE:To improve the convenience for use by transferring a designated number of occurrence values of a designated repeat group field in a record designated by a user program to the user program to update a transferred occurrence position storage area. CONSTITUTION:When a user program 10 requests record retrieval, a data base management system (DBMS) 20 returns the field value of a designated field to the reception area of the user program. If a repeat group field is designated, the designated number of occurrence values are returned. The user program 10 requests occurrence retrieval in each repeat group field for the purpose of retrieving residual occurrence values of the repeat group field in the taken-out record. When the occurrence retrieval request comes, the DBMS 20 transfers the designated number of untransferred occurrence value of the designated repeat group field to the use program 10. The number of actually transferred occurrence values is reported because the number of transferred occurrence values may reach the designated value.

23. 发明专利

JPS61151754A DATA BASE RECOVERY PROCESSING SYSTEM 失效
公开(公告)号：JPS61151754A
公开(公告)日：1986-07-10
申请号：JP27298884
申请日：1984-12-26
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MOGI KEIJI , MUTO HIDEO , FUKUSHIMA SHINICHI
IPC分类号： G06F3/06 , G06F12/00
摘要： PURPOSE:To recover quickly a data base at physical medium fault of the data base by controlling the parallel execution with a data base updating section in the unit of an analysis processing section of log information and a physical data area. CONSTITUTION:The titled system is a recovering processing system for a new physical medium 5 in which backup data 7 is copied to restore the medium before acquisition of log information after a faulty physical medium 6 is replaced. That is, a recovery processing control section 1 acquires registration/ recovery log classification storage areas 17, 18 for buffers secured by a data base buffer management section 4 and a log classification storage management table 10 and sets pointers 12, 15 to each log classification area. Then a task of a data base updating section 3 corresponding to each line of the table 10 is produced and waited. Then a task of a log analysis section 2 is generated and started. When the task of the analysis section 2 and the processing section 3 waits an I/O, they are in the waiting state, and when the control is restored to the control section 1, a proper task subjected to POST is selected and started.

24. 发明专利

JPH10154900A METHOD AND SYSTEM FOR ANALYZING FAILURE OF PRINTED BOARD FOR MOUNTING ELECTRONIC DEVICE 失效
公开(公告)号：JPH10154900A
公开(公告)日：1998-06-09
申请号：JP31341596
申请日：1996-11-25
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST
发明人： OCHIAI TATSUO , TABUCHI HIDEKI , YAMADA YU , KUWABARA YOSHIHIRO , MOGI KEIJI
IPC分类号： H05K13/08 , G05B13/02 , G05B23/02
摘要： PROBLEM TO BE SOLVED: To reduce labor required for failure analysis or preparation thereof by making the input layer of a neural network to correspond with test items of test results for a printed board and making the output layer to correspond with the failure index of devices mounted on the printed board thereby estimating a failed device. SOLUTION: A neural network 110 comprises a hierarchical feedforward network including an input layer 111, an intermediate layer 112 and a output layer 113 wherein engineeringly simulated neural cells, i.e., neurons 114-116, are information processing units. One-and-one correspondence is present between each neuron 114 constituting the input layer 111 of the neural network 110 and each item in the item column 102 of test result list 101 of a printed board for mounting electronic devices. A failed device is estimated by making each neuron 116 constituting the output layer 113 of the neural network 110 to correspond with each number in the number column 121 of analyzed parts list 120 of the printed board for mounting electronic devices.

25. 发明专利

JPH06139222A NEURO COMPUTER 失效
公开(公告)号：JPH06139222A
公开(公告)日：1994-05-20
申请号：JP29244992
申请日：1992-10-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OCHIAI TATSUO , SHIBATA KATSUNARI , ASAI MITSUO , SATO YUJI , SAKAGUCHI TAKAHIRO , HASHIMOTO MASA , TAKAYANAGI HIROSHI , MOGI KEIJI , OKABASHI TAKUO , KUWABARA YOSHIHIRO
IPC分类号： G06F15/16 , G06F15/177 , G06F15/18 , G06F15/80 , G06G7/60 , G06N3/06 , G06N3/10 , G06N99/00
摘要： PURPOSE:To speed up the execution of a neural network by inhibiting an in- neuron memory from being rewritten with a rewrite instruction to the memory according to the value that a specific internal signal indicates. CONSTITUTION:A data arithmetic circuit 107 performs the arithmetic operation of neurons and outputs arithmetic state signals 120-123 to a group control circuit 109. The arithmetic state signals 120-123 are processed so that group conditions are shown, and their value is written in a condition code register(CCR) 113. The output of the CCR 113 is selected by a selector 114 and group information is taken in a group flag group 115. The output of the group flag group 115 is led to an OR gate 116, whose outputs are all sent to an AND gate 118 to generate an internal memory write acknowledgment signal 128. Consequently, the arithmetic result of only a grouped neuron circuit 101 is written in an internal memory group 108.

26. 发明专利

JPH06139049A PARALLEL DATA PROCESSOR 失效
公开(公告)号：JPH06139049A
公开(公告)日：1994-05-20
申请号：JP29244392
申请日：1992-10-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OKABASHI TAKUO , ASAI MITSUO , SHIBATA KATSUNARI , SATO YUJI , HASHIMOTO MASA , SAKAGUCHI TAKAHIRO , TAKAYANAGI HIROSHI , MOGI KEIJI , OCHIAI TATSUO , KUWABARA YOSHIHIRO
IPC分类号： G06F7/38 , G06F7/53 , G06F15/18 , G06G7/60 , G06N99/00
摘要： PURPOSE:To advance an arithmetic operation by an entire device without operating a processing for an overflow by returning the maximum value to be expressed without generating the overflow at the time of processing data in which more than one results of the computing element of a parallel arithmetic processing unit overflow, and advancing the arithmetic operation by using the result. CONSTITUTION:An arithmetic element is constituted of a register file 1, memory 2 which stores the weight value of a neuron, shifter 3, ALU 5, and multiplier 7. Then, when the positive overflow of the arithmetic result is generated, the arithmetic operation is continued by using the positive maximum value to be expressed by the computing element as the arithmetic result, and when negative overflow of the arithmetic result is generated, the arithmetic operation is continued by using the additional maximum value to be expressed by the computing element as the arithmetic result. An overflow circuit 6 outputs 7FFFFFFFHEX at the time of the generation of the positive overflow, and outputs 8OOOOOOOHEX at the time of the generation of the negative overflow. A rounding circuit 4 operates a rounding in a zero direction at the time of executing an arithmetic right-shift by a shifter 3.

27. 发明专利

JPH06139375A PARALLEL DATA PROCESSOR 失效
公开(公告)号：JPH06139375A
公开(公告)日：1994-05-20
申请号：JP29244792
申请日：1992-10-30
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： OKABASHI TAKUO , SHIBATA KATSUNARI , ASAI MITSUO , SATO YUJI , SAKAGUCHI TAKAHIRO , HASHIMOTO MASA , OCHIAI TATSUO , KUWABARA YOSHIHIRO , TAKAYANAGI HIROSHI , MOGI KEIJI
IPC分类号： G06F15/16 , G06F15/18 , G06F15/80 , G06G7/60 , G06N99/00
摘要： PURPOSE:To miniaturize the address control part of a SIMD type parallel data processor to be used for a neuro computer and to attain the high speed of the address control. CONSTITUTION:An address pointer 1a for address control is provided on a control part 1. A register 1b retreating the address before update when the address pointer 1a is updated is provided on a control part 1. The information on a retreating register 1b is used as an address. Thus, a data processing part 3 is miniaturized by the concentration of the address control to the control part 1, the reduction in cost and the improvement of performance can be performed. By the use of the retreating register 11b, the high speed of the address control is attained and performance can be imp roved.

28. 发明专利

JPH06139217A HIGHLY PRECISE PROCESSING UNIT AND METHOD 失效
公开(公告)号：JPH06139217A
公开(公告)日：1994-05-20
申请号：JP29116492
申请日：1992-10-29
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： HASHIMOTO MASA , SAKAGUCHI TAKAHIRO , SATO YUJI , SHIBATA KATSUNARI , ASAI MITSUO , KUWABARA YOSHIHIRO , TAKAYANAGI HIROSHI , OKABASHI TAKUO , OCHIAI TATSUO , MOGI KEIJI
IPC分类号： G06F15/18 , G06G7/60 , G06N99/00
摘要： PURPOSE:To perform a highly precise arithmetic processing by a neuro com puter, which performs fixed-point and single-precision arithmetic processing without increasing a circuit scale and lowering the arithmetic processing speed. CONSTITUTION:The neuro computer 10 consists of plural neuro boards 12 which perform neural network operation and a control board 11. Further, the control board 11 consists of a neural network controller 13 which controls the neuro computer 10, a control storage 15 which stores microprograms, and a global memory 16 which stores the values of input layer neurons, etc. Then the neural network controller 13 decodes and executes the microprogram codes stored in the control storage 15 to performs the arithmetic processing of neural network operation having higher precision than single precision.

29. 发明专利

JPH05143309A DEVICE FOR DESCRIBING DATA FLOW MODEL 失效
公开(公告)号：JPH05143309A
公开(公告)日：1993-06-11
申请号：JP30162491
申请日：1991-11-18
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： TAKEUCHI YOICHI , FUNABASHI SEIJU , NAKANO TOSHIHIKO , MOGI KEIJI
IPC分类号： G06F9/06
摘要： PURPOSE:To easily execute description relating to the set data of a data flow model in a control system and an information processing system. CONSTITUTION:In a hierarchical data flow model, a function for repeatedly extracting the elements of set data and a function for executing set operation are applied to an input port 124 for inputting data from the outside of the model and a function for forming set data from plural internal data is applied to an output port 126 for outputting data to the outside of the model. Thereby a virtual buffer for storing the set data and the description of repeated processing relating to the elements of the set data are made unnecessary. Since set operation such as the formation of a direct product set is executed between plural ports having respectively different nodes, the combination processing of set data or the like can easily be described. Since the input port having respective nodes extract the elements of the set data synchronously with the updating of time, description relating to time sequence data can easily be executed.

30. 发明专利

JPH06325011A NEUROCOMPUTER 失效
公开(公告)号：JPH06325011A
公开(公告)日：1994-11-25
申请号：JP11437793
申请日：1993-05-17
申请人： HITACHI LTD , HITACHI MICOM SYST KK
发明人： TAKAYANAGI HIROSHI , SAKAGUCHI TAKAHIRO , KUWABARA YOSHIHIRO , MOGI KEIJI , MIYASHITA HIROSHI , ASAI MITSUO
IPC分类号： G06F15/18 , G06G7/60 , G06N3/10 , G06N99/00
摘要： PURPOSE:To provide a high-speed neural computer system for simultaneously executing plural algorithms at a neural network by providing a buffer for performing data transfer with the other neurocomputer. CONSTITUTION:A neurocomputer 20 is provided with a buffer 18 for performing communication with the other neurocomputer. When a neurocomputer 20a transfers information inside of its own device itself to another computer 20b a control part 10a transfers data inside arithmetic parts 1-4 to a buffer 18a. Next, the data transferred to the buffer 18a are transferred to a buffer 18b of the neurocomputer 20b. When executing any neural net model combining different algorithms, the neurocomputers 20a and 20b partially take in charge of the algorithm processing, and processing results and progress at the respective neurocomputers are received each other. Thus, parallel processing is enabled.

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