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21. 发明专利

JPH10112190A NONVOLATILE FERROELECTRIC SUBSTANCE MEMORY 失效
公开(公告)号：JPH10112190A
公开(公告)日：1998-04-28
申请号：JP26406496
申请日：1996-10-04
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI MIKI , YOSHIDA HIROSHI , TANIGAWA HIROYUKI
IPC分类号： G11C14/00 , G11C11/22
摘要： PROBLEM TO BE SOLVED: To obtain a ferroelectric substance memory suitable for a low voltage operation by setting an accumulation potential to two values of a voltage higher than a power source potential and 0V at the time of rewriting information. SOLUTION: In an information rewriting operation, a word line W1 is activated in a state in which bit line pair BL1, BB1 are precharged to the half of a power source voltage Vcc. Potentials of 0V or Vcc are complementary held in accumulation parts SN(1, 1) SB(1, 1) and a signal voltage is generated in between the bit line pair BL1, BB1 by the activation of the work line W1. A sense amplifier SA1 amplifies this signal to hold it at the potential of 0V or Vcc. When a rewriting voltage is applied on the bit line pairs BL1, BB1, the rewriting of information is executed. Here, a voltage Vbh higher than a voltage in which the power source voltage Vcc and threshold voltages of switching transistors are added is applied as the rewriting voltage. Then, either the SN(1, 1) or the SB(1, 1) of the accumulation parts becomes an accululation potential near to the voltage Vbh.

22. 发明专利

JPH1097472A SYSTEM INCLUDING FERROELECTRIC MEMORY 失效
公开(公告)号：JPH1097472A
公开(公告)日：1998-04-14
申请号：JP25126296
申请日：1996-09-24
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TANIGAWA HIROYUKI
IPC分类号： G06F12/16 , G06F11/10 , G11C11/22 , G11C11/401 , G11C14/00 , G11C29/42
摘要： PROBLEM TO BE SOLVED: To provide the system, including the ferroelectric memory, which greatly reduce the probability that large damage to the system is caused by a soft error of the ferroelectric memory and neither decreases the operating speed nor increases the chip price. SOLUTION: In the ferroelectric memory 120, a rewriting inhibited area 122 where an OS(operating system) and application are stored and a rewriting permitted area 122 as a work area are set. The rewrite inhibited area 122 includes a parity bit area 125 and an error correcting process which uses it is performed almost once a day by a CPU 110. A correction processing start command is associated with a switch (including a power switch). In this constitution, even if the ferroelectric memory 120 malfunctions, the function of the system can be restored and there is not problems such as a decrease in operating speed and an increase in chip area unlike a case wherein an ECC circuit(error correcting circuit) is provided.

23. 发明专利

JPH098247A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH098247A
公开(公告)日：1997-01-10
申请号：JP17429695
申请日：1995-06-15
申请人： HITACHI LTD
发明人： HASEGAWA MASATOSHI , KAJITANI KAZUHIKO , TAKEUCHI MIKI , MATSUNO KATSUMI , NAGASHIMA YASUSHI
IPC分类号： G11C14/00 , G11C11/22 , G11C11/401 , G11C11/404 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE: To improve usefulness of a semiconductor storage device by programmably setting a nonvolatile section and volatile section of the storage device in corresponding to the kind of data to be handled. CONSTITUTION: A semiconductor storage device is constituted so that the storage device can have such a large storage capacity as 1G bits as a whole and, for such an application that access is made 8 by 8 bits, the storage device can be utilized as a storage device of about 128 M bytes. The plate voltage VPL supplied to the plate electrode of each of 64 memory mats is adjusted so that such a voltage as 0V of VSS can be set to such an intermediate voltage of VCC /2. The eight memory mats (hatched mats) are operated as an ordinary DRAM by setting their voltages VPL to VPL=VSS and used as a volatile area. The remaining memory mats are operated as a FERAM by setting their voltages VPL to VPL=VCC /2 and used as a nonvolatile area.

24. 发明专利

JPH07334409A MEMORY SYSTEM 失效
公开(公告)号：JPH07334409A
公开(公告)日：1995-12-22
申请号：JP12341294
申请日：1994-06-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： TAKEUCHI MIKI , HORIGUCHI SHINJI , AOKI MASAKAZU , SAKATA TAKESHI , TANAKA HITOSHI , MATSUNO KATSUMI
IPC分类号： G11C11/407 , G06F12/00 , G06F13/16 , G11C7/10 , G11C11/401 , G11C11/409
摘要： PURPOSE:To provide a memory system capable of evading the speed deterioration due to signal delay from an I/O circuit up to a memory block and the complexity of design even when size or a chip area is increased. CONSTITUTION:A memory chip Sys0 has plural memory array blocks Bi, each of which has an address buffer AB and an address counter AD.C and operates with its own clock, a control circuit CNTL0 synchronous with a clock CLK from an external device and a data I/O synchronizing circuit CLKMT0 including a buffer BF0 for executing speed modulation so as to synchronize serial data sent from the block B; with the clock CLK of the circuit CNTL0. The buffer BF0 is connected to the block Bi through a data bus I/O and an external clock signal line is not distributed up to the inside of the block Bi.

25. 发明专利

JPH07192476A FERROELECTRIC MEMORY 失效
公开(公告)号：JPH07192476A
公开(公告)日：1995-07-28
申请号：JP33086393
申请日：1993-12-27
申请人： HITACHI LTD
发明人： MATSUNO KATSUMI , NAKAGOME YOSHINOBU , TAKEUCHI MIKI , HORIGUCHI SHINJI , ETO JUN , AOKI MASAKAZU
IPC分类号： G11C14/00 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
摘要： PURPOSE:To obtain a non-volatile ferroelectric memory which is easy to manufacture, has a high SN ratio, and is suitable for increasing the integration density. CONSTITUTION:A reference potential is generated by a reference potential generating section 102 based on a signal potential of logic 1, 0, and stored in a potential storage section 103. In read-out operation, a reference potential is generated in a data line of one side through a potential supplying section 104 based on a stored potential, and information is detected by comparing the reference potential with a signal potential read out in the other data line. In this constitution, since polarization inversion of a dummy cell can be evaded at the time of read-out operation, deterioration caused by fatigue of a film can be suppressed. Also, since a dummy cell having the same structure and size as a memory cell in generating the reference potential, manufacturing is made easy, dispersion of a characteristic is made small, and a highly accurate reference potential can be generated.

26. 发明专利

JPH06215589A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH06215589A
公开(公告)日：1994-08-05
申请号：JP564193
申请日：1993-01-18
申请人： HITACHI LTD
发明人： MATSUNO KATSUMI , NAKAGOME YOSHINOBU , TAKEUCHI MIKI , AOKI MASAKAZU
IPC分类号： G06F12/16 , G11C16/02 , G11C16/06 , G11C17/00
摘要： PURPOSE:To obtain a semiconductor memory having the constitution capable of relaxing the limit of the access number of times which a nonvolatile memory has in particular related to the constitution of the semiconductor memory. CONSTITUTION:A part of the contents of the nonvolatile memory is copied in a volatile memory 2 previously. When a bit corresponding to an access request address exists in the volatile memory 2, the information is transferred between the volatile memory 2 and the outside. When not, the information is exchanged between the nonvolatile memory 1 and the volatile memory 2, and the information is transferred between the volatile memory 2 and the outside. Thus, the access number of times to the nonvolatile memory are reduced, and the limit of the access number of times which the nonvolatile memory has is relaxed, and the life of the memory is prolonged.

27. 发明专利

JPH0675933A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0675933A
公开(公告)日：1994-03-18
申请号：JP22830492
申请日：1992-08-27
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , WATABE TAKAO , NAKAGOME YOSHINOBU , AOKI MASAKAZU
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N3/063 , G06N3/08 , G06N99/00
摘要： PURPOSE:To provide an information processor which can obtain the desired function of a processor by means of the simple learning method of a neural network without previously executing logical design. CONSTITUTION:In the neural network of three hierarchical type, a connecting weight value between a second layer V2 and a third layer V0 is fixed and only the connecting weight value between a first layer V1 and the second layer V2 is changed by learning. The connecting weight value between the second layer V2 and the third layer V0 is widely distributed by an analog value from an exciting one to a suppressive one. Since the neural network of the three hierarchical type can be formed by learning between the two layers, learning can be realized with simple architecture suitable for VLSI, and the neural network by which complicated operation can be executed is provided since it has the structure of three layers.

28. 发明专利

JPH0561998A INFORMATION PROCESSOR 失效
公开(公告)号：JPH0561998A
公开(公告)日：1993-03-12
申请号：JP22398291
申请日：1991-09-04
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , AOKI MASAKAZU
IPC分类号： G06F15/18 , G06G7/60 , G06N3/04 , G06N99/00 , G11C11/54
摘要： PURPOSE:To obtain the general purpose system and the architecture which can acquire a function by the learning to give repeatedly the set of the desired input value and output value without performing the logical design in a custom way in a processor, inference machine and an associative memory to obtain the set of the desired input value and output value. CONSTITUTION:The resistance is serially added to a usual switching MOS transistor between a memory cell and a data line to a dynamic random access memory. The action to give an input value to the word line and the desired output value for it to a data line pair is performed repeatedly for the set of the different input value and output value. When a two-layer hierarchy type network is formed with the capacity value of the memory cell obtained as the result as the coupling weight value, the desired processor is obtained.

29. 发明专利

JPH0418755A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0418755A
公开(公告)日：1992-01-22
申请号：JP12111690
申请日：1990-05-14
申请人： HITACHI LTD
发明人： HISAMOTO MASARU , TAKEUCHI MIKI , TAKEDA EIJI
IPC分类号： H01L27/11 , G11C11/401 , H01L21/8242 , H01L21/8244 , H01L27/108
摘要： PURPOSE:To obtain a semiconductor device very high in degree of integration by a method wherein an SOI transistor is used, whereby an N-type transistor and a P-type transistor are arranged adjacent to each other without forming a well. CONSTITUTION:A silicon oxide layer 200 is formed on a P-type silicon substrate 100, a single crystal silicon layer, an oxide film layer, and a silicon nitride layer are deposited thereon, then active regions 30, 31, 40, and 41 are formed through patterning, and then a transistor is set in characteristics through the distribution of impurities in a channel section. Then, a gate oxide film 260 and contacts 130 and 140 are formed, ions are implanted into the contacts 130 and 140, a tungsten silicide is deposited and patterned into a gate 60. Furthermore, a gate oxide film 210 is formed. Then, a gate 50 and word wires 10 and 11 are formed the same as the gate 60, and a bit wire contact 20 and a contact 70 are provided to carry out a wiring. By this setup, an N-type and a P-type flip-flop data holder and a selection transistor are formed in the smallest layout.

30. 发明专利

JPS62274771A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPS62274771A
公开(公告)日：1987-11-28
申请号：JP11727786
申请日：1986-05-23
申请人： HITACHI LTD
发明人： TAKEUCHI MIKI , TAKEDA EIJI , ITO KIYOO
IPC分类号： H01L27/10 , G11C11/401 , H01L21/8242 , H01L27/108
摘要： PURPOSE:To realize higher integration while preventing the S/N from degrading by a method wherein the plates of capacitor sections are connected with each other inside a silicon substrate and the storage capacitor sections and switching element sections are both made three-dimensional. CONSTITUTION:A semiconductor memory of this design is constituted of a charge-storing capacitor 1 and switching MOS transistor 2, and the drain of the MOS transistor 2 is connected to a bit line 3 and the gate thereof to a word line 4. The capacitors 1 are so formed as to surround an Si layer at a certain depth or lower, and a region to serve as the capacitor 1 is represented by a hatched rectangle 16. Plates 9 are formed in grooves 17, and are connected with each other inside the substrate, with a rectangle 16 serving as a memory cell. Insulation between capacitors is established by an SiO2 layer 10 in the upper region, and by a P layer 5 in the lower region. The vertical MOS transistors 2 built along the hole serve as switches, allowing signal charges into or out of the capacitor 1.

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