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21. 发明专利

JPH02271448A ADDRESS CONTROL CIRCUIT 失效
公开(公告)号：JPH02271448A
公开(公告)日：1990-11-06
申请号：JP9357589
申请日：1989-04-13
申请人： FUJITSU LTD
发明人： WATANABE TOSHIAKI , SHINOMIYA TOMOHIRO , EZAKI YUTAKA , SOEJIMA TETSUO , IGUCHI KAZUO
IPC分类号： G06F12/16
摘要： PURPOSE:To inhibit the output by comparing a write address with a read address by a write address comparing means and a read address comparing means, thereby deciding an address value to be abnormal at the time of the discordance. CONSTITUTION:Assuming that a write address 0 (ADR0) from FIFOs 211 and 221 is applied to a comparator 231, the comparator 231 outputs '1' since all bits are coincident with each other. AND gate 232 is turned on, and ADR0 from the FIFO 221 is outputted to a data memory 13 and RAMs 311 and 321. When ADR0 is changed to ADR2 by noise or the like, ADR0 and ADR2 are stored in RAM 311 and 321 respectively. ADR0 and ADR2 are simultaneously outputted to a comparator 331 from RAMs 311 and 321 respectively by an inputted read timing instruction and compared with each other, and the comparator 331 outputs '0' since address values are different from each other. Then, an AND gate 332 is turned off, and ADR2 outputted from the RAM 321 is interrupted.

22. 发明专利

JPH02179141A SWITCH CONTROL SYSTEM 失效
公开(公告)号：JPH02179141A
公开(公告)日：1990-07-12
申请号：JP33136888
申请日：1988-12-29
申请人： FUJITSU LTD
发明人： SHINOMIYA TOMOHIRO , EZAKI YUTAKA , WATANABE TOSHIAKI , IGUCHI KAZUO , SOEJIMA TETSUO
IPC分类号： H04L12/28
摘要： PURPOSE:To improve communication efficiency by controlling plural control buffers storing the storage address of an ATM cell and a speech path switch and an input buffer based on the plural control buffers corresponding to the transmission destination of each input buffer and an asynchronous transfer mode(ATM) cell. CONSTITUTION:When an ATM cell is supplied to an input buffer 111, the storage address of the ATM cell to the input buffer 111 is stored to a control buffer 131 prepared by the output port with the ATM cell sent therefrom corresponding to each input buffer. A 1st control signal 141 reads the storage address data of the input buffer 111 stored respectively to the control buffer 131 in the unit of the output ports, applies the selection to control the speech path switch 121. Moreover, the storage address data of the input buffer 111 selected by the selection is supplied to the corresponding input buffer 111 to read the ATM cell. Thus, since waiting time can be eliminated, the communication efficiency is improved.

23. 发明专利

JPH0265344A PACKET SYNCHRONIZING CONTROL SYSTEM 失效
公开(公告)号：JPH0265344A
公开(公告)日：1990-03-06
申请号：JP21526288
申请日：1988-08-31
申请人： FUJITSU LTD
发明人： EZAKI YUTAKA , WATANABE TOSHIAKI , SHINOMIYA TOMOHIRO , SOEJIMA TETSUO
IPC分类号： H04L12/70
摘要： PURPOSE:To load packet synchronization without lowering the efficiency of a transmission path by changing a deciding condition for synchronization establishment and synchronization step-out in correspondence to the measured value of an idle packet rate. CONSTITUTION:A sent packet is decided by an idle packet deciding circuit 11 and an idle packet pulse is outputted to a counter 12. The output of the counter 12 is measured as an idle packet rate (an idle packet arrival number) (k). When an address setter 14 designates the addresses of a k-m.k-n table 15 in correspondence to the idle packet rate (k), contents (m) or (n) of the table are inputted through a register 16 or 17 to a packet synchronizing part 2. When a frame pattern inserted into an idle packet is detected continuously by the (m)-times in the packet synchronizing part 2, such a condition is decided as the synchronization establishment. When the packet having the frame pattern is not detected in the packet synchronizing part 2 even when that the (n)-packet is obtained, such a condition is decided as the synchronization step-out.

24. 发明专利

JP2001144804A METHOD AND DEVICE FOR SELECTING PATH OF COMMUNICATION NETWORK 失效
公开(公告)号：JP2001144804A
公开(公告)日：2001-05-25
申请号：JP32159199
申请日：1999-11-11
申请人： FUJITSU LTD
发明人： NAKAMICHI KOJI , EZAKI YUTAKA , SOMIYA TOSHIO , TAKASHIMA KIYONARI
IPC分类号： H04M3/00 , H04L12/701 , H04L12/707 , H04L12/803 , H04L12/851 , H04L12/56
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for selecting the path of a communication network, by which loads can be diffused and a network resource can efficiently by used. SOLUTION: A plurality of paths 21 and 22 are set between an input side node 10 and an output side node 12. In the path selection method of a communication network for converting a label with respect to a traffic received by the input side node and it is transferred to the output side node. The traffic received by the input side node is uniformly distributed into the plurality of paths in a communication element unit and they are transferred. Thus, the loads of the respective paths can be diffused and the inverse of the order of packets transmitted from the same terminal can be prevented in the output side node.

25. 发明专利

JPH07307745A EXCHANGE 失效
公开(公告)号：JPH07307745A
公开(公告)日：1995-11-21
申请号：JP31141394
申请日：1994-12-15
申请人： FUJITSU LTD
发明人： TOMONAGA HIROSHI , MATSUOKA NAOKI , KAWAI MASAAKI , WATANABE MIWAKO , KUROYANAGI TOMOJI , EZAKI YUTAKA , HAKUTA AKIRA , TAKECHI RYUICHI
IPC分类号： H04J3/00 , H04L12/02 , H04L12/70 , H04L12/823 , H04L12/931 , H04L12/935 , H04L12/951 , H04Q3/00 , H04Q11/00 , H04L12/28
摘要： PURPOSE:To miniaturize individual parts by separating a line correspondence part for housing plural lines into the individual parts and a common part and processing a part of the functions of the individual parts provided for the respective lines altogether in the common part. CONSTITUTION:This exchange 10 is the exchange for performing the exchange processing of a fixed length composed of transmission data and a cell header and is provided with the line correspondence part 3 for housing the plural lines and processing information from the respective lines by a cell unit. The line correspondence part 3 is provided with the individual parts 31 and the common part 32 and the individual parts 31 are respectively connected to the plural respective housed lines and respectively perform a cell processing. The common part 32 is connected to the respective individual parts 31 and processes cells processed in the respective individual parts 31 altogether. Also, it is also valid to provide a termination part 12, a cell synchronization part 13 and an interface part 38 in the individual parts 31 as additional components.

26. 发明专利

JPH07264194A LINE ASSOCIATED OPERATION DEVICE FOR ATM EXCHANGE 失效
公开(公告)号：JPH07264194A
公开(公告)日：1995-10-13
申请号：JP4743894
申请日：1994-03-17
申请人： FUJITSU LTD
发明人： MATSUOKA NAOKI , TOMONAGA HIROSHI , WATANABE MIWAKO , KUROYANAGI TOMOJI , EZAKI YUTAKA , HAKUTA AKIRA , KATO TSUGIO , NISHI TETSUYA , NAKAJIMA HIDENAO , FUJITA SHUHEI , WATANABE YOSHIKI
IPC分类号： H04Q3/00 , H04L12/14 , H04L12/28
摘要： PURPOSE:To make the size of the line associated operation device small. CONSTITUTION:A line associated operation section 3 processes information from a subscriber terminal equipment 1 connecting to a subscriber terminal equipment 1 in th unit of cells. An SDH termination section 12 terminals a synchronization digital hierarchy multiplexing hierarchically the capacity of a transmission line through which an electric signal converted by a photoelectric conversion section 11 is sent. A cell synchronization section 13 detects a synchronizing signal of a cell by applying error control to the cell based on header error control information written in a cell header. A header conversion section 18 converts a virtual path identifier written in the cell header into a virtual path identifier being a destination by referencing a conversion table 180a storing the virtual path identifier written in the cell header and a destination virtual path identifier with cross reference.

27. 发明专利

JPH06188897A SYSTEM SWITCHING SYSTEM FOR ATM EXCHANGE 失效
公开(公告)号：JPH06188897A
公开(公告)日：1994-07-08
申请号：JP33475192
申请日：1992-12-15
申请人： FUJITSU LTD
发明人： KATO MASABUMI , KATO YUJI , KATO TSUGIO , EZAKI YUTAKA , TAKECHI RYUICHI , HAJIKANO KAZUO , KIYONO NAOHISA , OBA YASUHIRO , NAKAATO AKIRA , WATABE YOSHIHIRO
IPC分类号： H04Q3/52 , H04L12/28 , H04Q11/04 , H04L12/48
摘要： PURPOSE:To switch systems without redundantly providing buffer capacity and increasing the number of system communication contact points even in the case of a multistage buffer type ATM speech path. CONSTITUTION:All the buffers of existent and reserve systems 51' are made empty corresponding to a system switching request, afterwards, an input cell a' is multicasted to an existent operating system 51 and the reserve system 51', the same cell flow is applied to both of systems, reading is performed on the same situation in both of systems, and a selector 53 selects the cell from the existent operating system as an output to respective outgoing lines #i (i=1, 2...m). An empty monitor part 52 monitors the empty state of the buffer sharing the outgoing line for each outgoing line xsii of the existent operating system and since the content of buffers in both of systems are coincident after all the buffers sharing the prescribed outgoing line xsii are simultaneously made empty, the system switching part 53 selects/outputs the cell from the reserve system. Afterwards, switching is similarly performed concerning the other outgoing line.

28. 发明专利

JPH05122405A CHARGING CONTROL SYSTEM CORRESPONDING TO MEDIUM 失效
公开(公告)号：JPH05122405A
公开(公告)日：1993-05-18
申请号：JP27929891
申请日：1991-10-25
申请人： FUJITSU LTD
发明人： KATO TSUGIO , SHIMOE TOSHIO , KATO YUJI , TOMONAGA HIROSHI , EZAKI YUTAKA
IPC分类号： H04M15/00 , H04L12/14 , H04L12/70
摘要： PURPOSE:To attain charging only for an effective cell even in the communication service for retransmission control. CONSTITUTION:Cells of the communication service performing no retransmission control like audio signals or picture signals identified by a cell identification part 2 are counted up in a counter part 1 to obtain a meter rate parameter of charging for the communication service. As for the cells of the communication service performing retransmission control like data, cells between the start and the end of a frame are counted by a frame detecting part 3 and it is identified whether cell abandonment occurs or not and only the number of cells in the frame where cell abandonment does not occur is counted up in the counter part 1 but the number of cells in the frame where cell abandonment occurs is not counted up there.

29. 发明专利

JPH0537548A MULTIPLEX STM/ATM CONVERSION SYSTEM 失效
公开(公告)号：JPH0537548A
公开(公告)日：1993-02-12
申请号：JP19415791
申请日：1991-08-02
申请人： FUJITSU LTD
发明人： SHIMOE TOSHIO , KATO YUJI , KATO TSUGIO , EZAKI YUTAKA , TOMONAGA HIROSHI
IPC分类号： H04J3/00 , H04L12/28 , H04Q11/04
摘要： PURPOSE:To reduce the cell processing delay time by deviating a byte number of information stored at information storage with respect to an adjacent channels. CONSTITUTION:In the case of a multiplex STM/ATM conversion circuit converting a synchronous transfer mode (STM) signal into an asynchronous transfer mode (ATM) signal, the information from the STM network is inputted to a mapping control means 1 in the unit of frames and the mapping control means 1 inputs at first the information to a control section 3. The control section 3 identifies the received information in the unit of frames for each time slot number (channel) and writes the information to a channel buffer 4 (4a-4c) corresponding to each channel for each time slot. In this case, the control section 3 writes a byte number while deviating stepwise between adjacent channels. Then the mapping means 2 applies ATM cell processing to the information stored in the channel buffer 4 by the information field of an ATM cell. As a result, the cell processing delay time is reduced.

30. 发明专利

JPH04329733A MONITOR SYSTEM FOR TRANSMISSION NETWORK 失效
公开(公告)号：JPH04329733A
公开(公告)日：1992-11-18
申请号：JP12863491
申请日：1991-04-30
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： EZAKI YUTAKA , FUJIMOTO TOSHIBUMI
IPC分类号： H04Q3/00 , H04L12/24 , H04L12/26 , H04L12/28
摘要： PURPOSE:To realize the monitor of an ATM transmission network able to measure a cell flow without increasing the circuit scale by providing an input/ output section, a timer, a memory and a traffic measuring section to the system. CONSTITUTION:An initial value for the entire device is set to an input output section 1. A traffic measurement section 4 continues the measurement when a preceding cell arrival time and arrival time interval in the memory 3 are not a lower limit at the arrival of a succeeding cell of a same identifier. The measurement is a gain implemented when the measurement allowable time is exceeded and the result is not outputted from the input output section 1. Thus, even when number of identifiers is increased, the system copes with it by having only to increase the capacity of the memory 3, the circuit scale is not affected and no error measurement result is outputted. When the arrival time interval between cells of the same identifier is less than the lower limit, number of times of violation is accumulated to the memory 3, the number of times of violation and its identifier are outputted from the input output section 1 at the end of the measurement to inform the time interval of the violation cell. Thus, the cell flow is accurately given.

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