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21. 发明专利

JPS62166624A VITERBI DECODER 失效
公开(公告)号：JPS62166624A
公开(公告)日：1987-07-23
申请号：JP795786
申请日：1986-01-20
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , KATO TADAYOSHI , MORIWAKE MASARU
IPC分类号： H03M13/23
摘要： PURPOSE:To realize a small-sized economic Viterbi decoder, by constituting the Viterbi decoder by using the same kind of ICs in such a way that ACS circuits to be integrated in corresponding with the number of a node whose internal state is in transition are selected and numbers of wiring among ICs and input-output signals lines of each IC are reduced. CONSTITUTION:Selectors 7 and 8 are made to make selecting operations by operation mode setting signals and select the inputs of the I-th and (I+1)-th ACS circuits 1 and 2 at the LSIs at the positions corresponding to both end sides of an ACS circuit array. The selectors 7 and 8 use the selected inputs as the one-side inputs of the 2I-th, (2I+1)-th, 2(I+1)-th, and [2(I+1)+1]-th ACS circuits 3-6 and cause the ACS circuits to operate as four pieces of ACS circuits. At the other LSIs, the selectors 7 and 8 select the outputs of the I-th and (I+1)-th ACS circuits 1 and 2 and use the selected outputs as the one-side inputs of the 2I-th, (2I+1)-th, 2(I+1)-th, and [2(I+1)+1]-th ACS circuits 3-6 so as to cause the ACS circuits 3.6 to operate as 6 pieces of ACS circuits. Moreover, a branch metric calculation circuit 9 carries out branch metric calcula tion by using code inputs IS and QS demodulated at a demodulation section and adds the calculates results to each ACS circuit.

22. 发明专利

JPS6251832A MARK REGISTER 失效
公开(公告)号：JPS6251832A
公开(公告)日：1987-03-06
申请号：JP19132285
申请日：1985-08-30
申请人： FUJITSU LTD
发明人： SHIMODA KANEYASU , YAMASHITA ATSUSHI
IPC分类号： H03M13/23
摘要： PURPOSE:To reduce the storage capacity by converting a test number of times of each path branched from a node for sequential decoding in a sequential decoder into a relative value below a predetermined value and storing the result. CONSTITUTION:The number of times of path test for the sequential decoding is stored in a storage means 1. The number of times of the path branched from the node connected with a path selected at the path test of the sequential decoding is read from the storage means 1 by an access means 2. A test number of time revision means 3 in response to the test number of time each path read in this way and the selected path identification information converts the test number of time of each path into a relative value being a predetermined value or below and the relative value is stored in a corresponding storage area from which the test number of times is read prior to the generation of the relative value to update the content.

23. 发明专利

JPS6121637A Timing generating device 失效
标题翻译：时序生成装置
公开(公告)号：JPS6121637A
公开(公告)日：1986-01-30
申请号：JP14136784
申请日：1984-07-10
申请人： Fujitsu Ltd
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI
IPC分类号： H04J3/06 , G06F13/42 , H04B7/15 , H04B7/212
CPC分类号： G06F13/4221
摘要： PURPOSE:To attain the processing with flexibility such as using a part where a program of identical patterns is used repetitively as a subroutine by decoding control information relating to the memory access order read from a storage means to change the order of memory access and generating a timing signal based on the timing information read from the storage means. CONSTITUTION:A timing generating circuit 3 by a frame pulse is started, an instrucion decoder 301 reads an instruction word from a RAM2, its content is decoded and when the instruction word is a JMP instruction of a command mode, a jump destination address is designated to the RAM2 via an address counter 304 to read to the instruction word of the jump destination address at the next cycle. When the instruction word is in, e.g., a RAM count mode, an output port number included in the instruction word is set to a decoder 303 to designate an output port from which the timing pulse is outputted. The timing pulse length of the content of the next address is set to the counter 302 at the next cycle and an output is transmitted from a designated output port.
摘要翻译：目的：通过解码与从存储装置读取的存储器存取顺序相关的控制信息来重复地使用相同模式的程序作为子程序的部分，以灵活性来实现处理，以改变存储器访问的顺序并产生基于从存储装置读取的定时信息的定时信号。构成：通过帧脉冲开始定时发生电路3，指令解码器301从RAM2读取指令字，对其内容进行解码，当指令字为命令模式的JMP指令时，指定跳转目标地址通过地址计数器304发送到RAM2，以在下一个周期读取跳转目标地址的指令字。当指令字处于例如RAM计数模式时，包括在指令字中的输出端口号被设置到解码器303以指定输出定时脉冲的输出端口。在下一个周期将下一个地址的内容的定时脉冲长度设置到计数器302，并且从指定的输出端口发送输出。

24. 发明专利

JPS60173930A PIPELINE PROCESSING VITERBI DECODER 失效
公开(公告)号：JPS60173930A
公开(公告)日：1985-09-07
申请号：JP2848884
申请日：1984-02-20
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI , KURIHARA HIROSHI
IPC分类号： G06F11/10 , H03M13/23 , H03M13/41
摘要： PURPOSE:To improve the throughout by executing in parallel the path metric calculation and comparison. CONSTITUTION:The path metric value of added output selected by selectors 37, 38 is compared and path selecting information is outputted to a comparator 41 in adding the next path metric value by adders 31-34. Since the path metric value of the preceding added output is compared by the comparator 41, the pipeline processing is attained.

25. 发明专利

JPS60144026A VITERBI DECODER 失效
公开(公告)号：JPS60144026A
公开(公告)日：1985-07-30
申请号：JP65184
申请日：1984-01-06
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , KATOU TADAYOSHI
IPC分类号： H03M13/23 , H03M13/41 , H03M13/12
摘要： PURPOSE:To inhibit a metric calculation to a dummy bit without increasing a circuit scale by providing a code converting part for converting an inversion and a non-inversion of a receiving code by receiving a metric calculation inhibiting signal, on a branch metric calculating circuit. CONSTITUTION:At the time of a branch metric calculation, a code is converted immediately before adding a code, dummy bits QR and -QR are set to the same value, and an equal effect to that which has inhibited a metric calculation is given. Code converting parts 767, 768 are added to a branch metric calculating part 76. The code converting part 767 converts a code so as to be I=-I only when a metric calculation inhibiting signal INH from a dummy bit inserting part is active, and outputs I and -I as they are in other case. The code converting part 768 also executes the same. The dummy bit inserting part knows an inserting position of a dummy bit, therefore, the inhibiting signal INH to be inputted to the code converting parts 767, 768 from said part can be generated easily.

26. 发明专利

JPS59123303A Agc control system in receiver for receiving burst wave 失效
标题翻译：用于接收冲击波的接收器中的AGC控制系统
公开(公告)号：JPS59123303A
公开(公告)日：1984-07-17
申请号：JP22927182
申请日：1982-12-29
申请人： Fujitsu Ltd
发明人： TAKENAKA SADAO , YAMASHITA ATSUSHI , ISHIKAWA HITOSHI
IPC分类号： H04B1/16 , H03G3/20
CPC分类号： H03G3/3052
摘要： PURPOSE:To make levels of each burst receiving wave uniform by sectioning an output of a receiving level detector corresponding to the burst number and setting an AGC control voltage to the next burst receiving wave given with the same burst number. CONSTITUTION:A burst receiving wave B2 passing through a variable gain circuit 1 is detected at a detector 2 and then led to an A/D converter 4 via a filter 3. The A/D converter 4 converts a detected level of the burst receiving wave B2 corresponding to the timing indication from a timing forming circuit section 9 into a digital signal and supplies the result to a data processor 5. In this case, the timing forming circuit section 9 communicates a burst number to the data processor. The data processor calculates a control voltage and gives its data and the burst number to a memory 6. The data in the memory 6 is read to the next burst receiving wave B2 so as to control the variable gain device 1.
摘要翻译：目的：通过对与突发数相对应的接收电平检测器的输出进行分频，并将AGC控制电压设置为以相同脉冲串数给出的下一个突发接收波，来使每个脉冲串接收波的电平均匀。构成：在检测器2处检测通过可变增益电路1的脉冲串接收波B2，然后经由滤波器3被引导到A / D转换器4.A / D转换器4将检测到的脉冲串接收波电平 B2对应于从定时形成电路部分9的定时指示为数字信号，并将结果提供给数据处理器5.在这种情况下，定时形成电路部分9将数据传送到数据处理器。数据处理器计算控制电压并将其数据和突发数量提供给存储器6.存储器6中的数据被读取到下一个突发接收波B2，以便控制可变增益设备1。

27. 发明专利

JPH07226696A FREQUENCY HOPPING TYPE SPREAD SPECTRUM COMMUNICATION METHOD 失效
公开(公告)号：JPH07226696A
公开(公告)日：1995-08-22
申请号：JP1561194
申请日：1994-02-10
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI
IPC分类号： H04B1/713 , H04B1/7143 , H04J13/06
摘要： PURPOSE:To reduce the circuit scale and dissipated power by making unequal the intervals of the output frequencies of a variable frequency oscillator for frequency hopping and transmitting a chip which is set so that the empty within a spread band width may be minimum corresponding to it. CONSTITUTION:A frequency division is performed for the output (original oscillation frequency f0) of a high frequency oscillator 11 in a variable frequency divider 12 and a desired output frequency f1 is obtained. The original oscillation frequency f0 is the same as the highest hopping frequency, the circuit scale is small and the original oscillation frequency of an oscillator is not switched, frequency switching time becomes virtually zero. When the interval of the hopping frequency is wide, chip rate is increased and the number of chip to be transmitted within fixed time is increased. When the interval of the hopping frequency is narrow, the chip rate is lowered and the number of chip to be transmitted within fixed time is reduced. Thus, frequency use efficiency is improved.

28. 发明专利

JPH05219008A SPREAD SPECTRUM COMMUNICATION SYSTEM 失效
公开(公告)号：JPH05219008A
公开(公告)日：1993-08-27
申请号：JP1653292
申请日：1992-01-31
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI , USHIYAMA TAKAYUKI , MATSUYAMA KOJI , OIDE TAKAYOSHI
IPC分类号： H04J13/00 , H04B1/7097 , H04B1/715
摘要： PURPOSE:To increase the number of channels even when there are lines having large interference as to the spread spectrum communication system which uses a direct spread system or frequency hopping system. CONSTITUTION:In the spread spectrum communication system wherein code sequences for direct spreading or frequency hopping which are different corresponding plural lines are assigned, the spread band width Wdn of the direct spread system or the band width Wdn of the frequency hopping system of the transmission part 6 of a key station 2 is increased for a down line from the key station 2 to a mobile station 1 where interference is large, and the spread band width Wup of the direct spread system or the band width Wup of the frequency hopping system of the transmission part 3 of the mobile station 1 is set narrow for an up line from the mobile station 1 to the key station 2 where interference is small.

29. 发明专利

JPH05113834A DIGITAL SIGNAL PROCESSING SYSTEM 失效
公开(公告)号：JPH05113834A
公开(公告)日：1993-05-07
申请号：JP27587591
申请日：1991-10-24
申请人： FUJITSU LTD
发明人： TAKENAKA TETSUYOSHI , YAMASHITA ATSUSHI
IPC分类号： G06F1/08
摘要： PURPOSE:To provide the digital signal processing system which wastes no electric power when a throughput quantity varies with time. CONSTITUTION:The digital signal processing system 10 is equipped with a means 1 which detects the throughput of the digital signal processing system 10 and a clock speed control means 2 which is driven with the detection signal of the throughput detecting means 1 and controls the speed of a clock for operating this system 10, and the clock speed control means 2 controls the clock so that its frequency is low when the signal throughput of the system is small or high when large.

30. 发明专利

JPH0522255A CONSECUTIVE CODING SYSTEM 失效
公开(公告)号：JPH0522255A
公开(公告)日：1993-01-29
申请号：JP17487791
申请日：1991-07-16
申请人： FUJITSU LTD
发明人： YAMASHITA ATSUSHI
IPC分类号： H04L1/00
摘要： PURPOSE:To save the circuit scale of an external code decoder by reducing number of error patterns to be corrected by the external code decoder so as to enhance the coding rate of an external code. CONSTITUTION:A transmission data, a block length of the entire parity, a parity bit number n and an error pattern with a high probability of production are decided for a polynomial used for generating an external code in response to an error pattern produced after decoding of an inner code on a receiver side, the error pattern is divided by the polynomial whose degree is n and polynomials whose residue differs from each other. A sender side 100 is provided with an external code coder 11 which uses a parity generating circuit 111 to generate the parity code from the polynomial, to synthesize it with a transmission data and to send the result to an inner code coder. A receiver side 200 is provided with an external code decoder 22, which receives a code from the inner code decoder, adds position information of an error block based on a syndrome generated by a syndrome generating circuit 221 and a bit error pattern in an I' block and uses a correction pattern generator 222 to generate a correction pattern and adds the result to an input code subject to phase locking.

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