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21. 发明专利

JPS6275868A CONTROL SYSTEM FOR JOB REQUEST BETWEEN INFORMATION PROCESSORS 失效
公开(公告)号：JPS6275868A
公开(公告)日：1987-04-07
申请号：JP21708785
申请日：1985-09-30
申请人： FUJITSU LTD
发明人： KIMOTO TAKASHI , NAKAMURA YOSHIHIRO , FUKATSU SADAO , WATABE NOBUO , SATO KEIJI
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To avoid the concentration of requests to a specific device by delivering the search requests to each device from a requester device to select a device to be requested from the sent-back state information and at the same time informing the release of lock to other devices. CONSTITUTION:A packet transmission/reception control part 4 has an interface with a network 10 and uses a packet to perform the transfer of information between personal computers. A job request part 5 starts a state collecting part 6 when a request is given to another personal computer. Then the part 6 analyzes the state information packet given from a requester that answered a search request and informs the state of this analysis to a request receiver deciding part 9. Thus the part 9 decides a job request receiver based on the information given from the part 6. A state information request part 7 sends a state information request packet to the personal computer at the request receiver side. Then the part 5 request the personal computer at the request receiver side for job processing. A lock releasing part 8 transmits the lock release information to the personal computers excepting for the one at the request receiver side.

22. 发明专利

JPS622745B2 失效
公开(公告)号：JPS622745B2
公开(公告)日：1987-01-21
申请号：JP15309380
申请日：1980-10-31
申请人： FUJITSU LTD
发明人： SATO KEIJI , NAKAMURA YOSHIHIRO , MITA TERUYOSHI , KITANO YOSHIHIRO , YATSUHOSHI AKIMASA
IPC分类号： H04L12/42

23. 发明专利

JPS623525A TWO-WAY WIRED LOGIC OPERATION CIRCUIT 失效
公开(公告)号：JPS623525A
公开(公告)日：1987-01-09
申请号：JP14279685
申请日：1985-06-29
申请人： FUJITSU LTD
发明人： INOUE KOICHI , SATO KEIJI , IKESAKA MORIO
IPC分类号： H03K19/00
摘要： PURPOSE:To obtain a logic operation circuit operated in two-way with simple constitution by connecting a NOR circuit and a wired logic circuit in cascade, connecting them reversely and applying NOR operation. CONSTITUTION:A NOR circuit 3(U3) and a wired OR circuit 1(U1) are connected in cascade and circuits U2, U4 are connected and the circuit connections are connected in anti-parallel. Points X, Y are used as signal input/output terminals. Further, the feedback connection is applied so that the input and output of one wired logic operation circuit are subject to be in operation by the other NOR circuit. In setting X=Y='1' at first, since one input to both the circuits U3, U4 is logical 1, the relation of x=y='0' is obtained. When the point X is at '0', both the inputs to the circuit U4 are logical 0 and the level of the point (y) is logical 1. Thus, the output of the circuit U2 is logical 0. The level of the point Y is logical 0 and the logic value at the point X is delivered to the point Y. When '1' is set to the point X and '0' is set to the point Y after X=Y='1' is set to the point X and '0' is set to the point Y after X=Y='1' conversely, the point X is logical 0 and the value of Y is delivered by the similar operation.

24. 发明专利

JPS61246868A SYNCHRONIZATION CONTROL METHOD 失效
公开(公告)号：JPS61246868A
公开(公告)日：1986-11-04
申请号：JP8773185
申请日：1985-04-24
申请人： FUJITSU LTD
发明人： INOUE KOICHI , SATO KEIJI , IKEZAKA MORIO
IPC分类号： G06F15/16 , G06F15/177
摘要： PURPOSE:To attain the weight state detection of each processor and the next step start control through one signal line by connecting plural processors executing the prescribed processing independently and a control part controlling each processor in terms of wired logic. CONSTITUTION:A delayed synchronizing signal oscillator circuit DL 4 installed on the control part 3 and respective processors 1-1-1-n are controlled through the signal line 2 connected by wired logical elements U1 and U2. When a wait instruction is executed, each flip-flop FF 2 is set to open the output of the element U2, because each processor is synchronous. When all elements U2 connected to the signals line 2 are opened, the FF 1 of the control part 3 is set, and the signal line 2 comes to L level through an AND gate G1 and the element U1. The the FF 3 of each processor is set, and the DL 4 is operated after the prescribed time. Then the FF 4 is set through the gate G1, the signal line 2 and the gate G2 to start the next step.

25. 发明专利

JPS6119064B2 JPS6119064B2 - 失效
公开(公告)号：JPS6119064B2
公开(公告)日：1986-05-15
申请号：JP7080780
申请日：1980-05-29
申请人： Fujitsu Ltd
发明人： SATO KEIJI , YAMAGUCHI NAOKI , ODA MANABU , TARUI YASUNORI , ISHII YOSHINORI
IPC分类号： G06F9/38 , G06F15/16
CPC分类号： G06F9/3836 , G06F9/3867 , G06F9/3885

26. 发明专利

JPH04340921A PHOTOSEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH04340921A
公开(公告)日：1992-11-27
申请号：JP11302791
申请日：1991-05-17
申请人： FUJITSU LTD
发明人： SATO KEIJI , SODA HARUHISA
IPC分类号： G02B6/12 , G02F1/01 , H01S5/06
摘要： PURPOSE:To provide the photosemiconductor device by realizing high-frequency modulation higher than the modulation frequency of an electric driving system and increasing the transmission capacity. CONSTITUTION:A DFB laser part 4 which oscillates in single longitudinal mode, a Y-shaped branch waveguide 8 which divides the light from the DFB laser part 4 to two waveguides 6a and 6b, and a Y-shaped multiplexing waveguide 10 where the two waveguides 6a and 6b come together are provided on the same semiconductor substrate 2. The two waveguides 6a and 6b are provided with clock signal modulation parts 12a and 12b having electrodes applied with clock signals as electric signals and data signal modulation parts 14a and 14b having electrodes applied with data signals as electric signals.

27. 发明专利

JPH04329037A ANALOG LIGHT RECEIVING ELEMENT 失效
公开(公告)号：JPH04329037A
公开(公告)日：1992-11-17
申请号：JP9884991
申请日：1991-04-30
申请人： FUJITSU LTD
发明人： SATO KEIJI
IPC分类号： H04B10/40 , H04B10/2507 , H04B10/50 , H04B10/54 , H04B10/564 , H04B10/58 , H04B10/60 , H04B10/67 , H04B10/69
摘要： PURPOSE:To reduce the adjustment load relating to a high frequency cable and the effect of a high frequency connector or the like onto the cable by reducing a distance between a matching device for an electric signal and its amplifier section to the utmost and to improve a frequency response characteristic of a reception processing unit with respect to an analog light receiving element, especially a preamplifier module structure for analog transmission optical communication processing an electric signal whose frequency is several hundreds MHz-several GHz. CONSTITUTION:The preamplifier is provided with a photoelectric conversion means 11 converting an analog transmission light LA into an electric signal SA, an output means 12 outputting an electric signal SA to a signal transmission means 15, a matching means 3 matching the impedance between the signal transmission means 15 and the output means 12, and the photoelectric conversion means 11, the output means 12 and the matching means 13 are stored in one and same container means 14 having an optical incidence window.

28. 发明专利

JPH04319695A ERROR ADJUSTMENT CIRCUIT OF TIME MEASUREMENT MECHANISM 失效
公开(公告)号：JPH04319695A
公开(公告)日：1992-11-10
申请号：JP8799391
申请日：1991-04-19
申请人： FUJITSU LTD
发明人： YAO MITSUYOSHI , SATO KEIJI
IPC分类号： G04G3/02 , G04G3/00 , G06F1/14
摘要： PURPOSE:To enable realization of a highly accurate, small sized and economical clocking mechanism by predicting actual oscillation frequency of an oscillator based on external conditions, and by obtaining and accumulating the error of the predicted frequency parting from the nominal frequency. CONSTITUTION:In a clocking mechanism 11 which measures time, based upon an oscillator 1 having a specified nominal frequency, a prediction means 2 predicts actual oscillation frequency of the oscillator 1 and a calculation means 3 calculates error of the predicted frequency given by the prediction means 2, against the nominal frequency, at every specific time shown by the clocking means 11. Also, an accumulation mean 4 accumulates the error calculated by a calculation means 3 and an adjustment means 5 adjusts the time shown by the clocking mechanism 11, based on the nominal frequency of the oscillator 1 and the accumulated error from the accumulation means 4, in order to output the correct time.

29. 发明专利

JPH04276666A SEMICONDUCTOR PHOTODETECTOR AND ITS ASSEMBLY METHOD 失效
公开(公告)号：JPH04276666A
公开(公告)日：1992-10-01
申请号：JP3820591
申请日：1991-03-05
申请人： FUJITSU LTD
发明人： SATO KEIJI
IPC分类号： H01L31/10
摘要： PURPOSE:To provide a rear incident-type semiconductor photodetector which can simplify the coupling and centering operation of an optical fiber and to provide an assembly method using it while a fully automatic assembly process equipped with an optical fiber in future is taken into consideration. CONSTITUTION:A p-type impurity region 4 is formed on the surface of an n-type semiconductor substrate 2 to form a p-n junction face. A passivation film 6 is formed on the surface of the n-type semiconductor substrate 2 and the p-type impurity region 4. A p-side electrode 8 is formed via a contact window which has been opening in the passivation film 6 on the p-type impurity region 4. This invention is featured by a point that the p-side electrode 8 is formed in a position dislocated form the central part of the p-n junction face, i.e., a photodetection face, between the n-type semiconductor substrate 2 and the p-type impurity region 4.

30. 发明专利

JPH0159780B2 失效
公开(公告)号：JPH0159780B2
公开(公告)日：1989-12-19
申请号：JP17438480
申请日：1980-12-10
申请人： FUJITSU LTD
发明人： SATO KEIJI , NAKAMURA YOSHIHIRO , MITA TERUYOSHI , KITANO YOSHIHIRO , YATSUHOSHI AKIMASA
IPC分类号： H04L1/22 , H04L12/437

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