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21. 发明专利

JP2007017231A Multichip module 有权
标题翻译：多模块模块
公开(公告)号：JP2007017231A
公开(公告)日：2007-01-25
申请号：JP2005197518
申请日：2005-07-06
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI , FUJINO TSUYOSHI
IPC分类号： G01R31/28 , H01L25/04 , H01L25/18
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/4903 , H01L2224/49113 , H01L2924/13091 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a multichip module capable of inspecting the signal terminal which is the subject of the chip-to-chip wiring without increasing the number of terminals to be arranged outside of the package. SOLUTION: Between the semiconductor chips 22 and 23, respective pads 24 and 25 are mutually connected with the chip-to-chip wiring 26. The semiconductor chip 23, the pad 25 of which is functions as an output terminal is named an inspection objective chip, and the other is named an inspection performing chip 22. In the inspection objective chip 23, the level of the pad 25 is set high by turning the FETs 42 and 43 ON via the transistor control register 46. In the inspection performing chip 22, to the constant current source 32 arranged between the pad 24 and the ground one of constant current source is selected by the current control register 33, and the threshold voltage of the comparator 30 is set up by the voltage control register 39 and the D/A converter circuit 38. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种多芯片模块，其能够检查作为芯片到芯片布线的对象的信号端子，而不增加要布置在封装外部的端子的数量。解决方案：在半导体芯片22和23之间，相应的焊盘24和25与芯片到芯片布线26相互连接。其作为输出端子的焊盘25的半导体芯片23被命名为检查对象芯片，另一个被称为检查执行芯片22.在检查对象芯片23中，通过晶体管控制寄存器46使FET42和43导通，将焊盘25的电平设置为高电平。在检查执行芯片22通过电流控制寄存器33选择布置在焊盘24和恒流源的接地之间的恒流源32，并且比较器30的阈值电压由电压控制寄存器39和 D / A转换器电路38.版权所有（C）2007，JPO＆INPIT

22. 发明专利

JP2007017230A Multichip module 有权
标题翻译：多模块模块
公开(公告)号：JP2007017230A
公开(公告)日：2007-01-25
申请号：JP2005197517
申请日：2005-07-06
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI , FUJINO TSUYOSHI
IPC分类号： G01R31/28 , H01L25/04 , H01L25/18
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48137 , H01L2224/49 , H01L2224/4903 , H01L2224/49113 , H01L2924/13091 , H01L2924/3011 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a multichip module capable of inspecting the signal terminal which is the subject of the chip-to-chip wiring without increasing the number of terminals to be arranged outside of the package. SOLUTION: Regarding the part where two semiconductor chips 22 and 23 keep their respective pads 24 and 25 mutually connected by the chip-to-chip wiring 26 in the multichip module 21, the voltage D/A converted by writing the data to the D/A setting register 45 of the threshold value inspection circuit 43 stored in the inspection chip 23 is impressed to the input terminal (pad 25), and the data of the register 45 is increased by the adder 50 for every prescribed value, when the output level of the input gate 34 is inverted, the operation circuit 52 stops the update of data written into the D/A setting resister 45. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种多芯片模块，其能够检查作为芯片到芯片布线的对象的信号端子，而不增加要布置在封装外部的端子的数量。解决方案：关于两个半导体芯片22和23通过多芯片模块21中的芯片到芯片布线26保持其相应的焊盘24和25的部分，通过将数据写入而转换的电压D / A 存储在检查芯片23中的阈值检查电路43的D / A设置寄存器45被施加到输入端（焊盘25），并且通过加法器50对每个规定值增加寄存器45的数据，当输入门34的输出电平反转，操作电路52停止写入D / A设定寄存器45的数据更新。（C）2007，JPO＆INPIT

23. 发明专利

JP2006295059A Semiconductor device and its manufacturing method 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006295059A
公开(公告)日：2006-10-26
申请号：JP2005117137
申请日：2005-04-14
申请人： Denso Corp , 株式会社デンソー
发明人： FUJINO TSUYOSHI , NODA SHINICHI , IMADA SHINJI
IPC分类号： H01L25/18 , H01L25/065 , H01L25/07
CPC分类号： H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/49175 , H01L2224/73265 , H01L2224/78301 , H01L2224/85181 , H01L2224/92247 , H01L2924/01079 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device obtained by cutting apart a semiconductor wafer having semiconductor elements formed in units of a chip, wherein heat-dissipating properties can be appropriately ensured in response to a structure. SOLUTION: A second semiconductor element 20 and a first semiconductor element 10 are sequentially laminated and mounted on an island 30, and both the semiconductor elements 10, 20 are adhered with adhesives 70. Further, both the semiconductor elements 10, 20 are electrically connected to a lead 40 by a bonding wire 70, and these are sealed with a mold resin 60. Here, the first semiconductor element 10 of an upper stage is configured as an aggregate of a plurality of (two or more) units of a chip T cut apart from a semiconductor wafer 200. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种通过切割具有以芯片为单位形成的半导体元件的半导体晶片而获得的半导体器件，其中可以根据结构适当地确保散热特性。解决方案：第二半导体元件20和第一半导体元件10依次层叠并安装在岛30上，并且两个半导体元件10,20都用粘合剂70粘合。此外，半导体元件10,20都是通过接合线70电连接到引线40，并且这些被模制树脂60密封。这里，上级的第一半导体元件10被构造为多个（两个或更多个）单元的集合体芯片T与半导体晶片200分离。版权所有（C）2007，JPO＆INPIT

24. 发明专利

JP2005327025A Output control system, output controller and host controller 审中-公开
标题翻译：输出控制系统，输出控制器和主机控制器
公开(公告)号：JP2005327025A
公开(公告)日：2005-11-24
申请号：JP2004143567
申请日：2004-05-13
申请人： Denso Corp , 株式会社デンソー
发明人： KAMIYA MASAHIRO , NODA SHINICHI , ISHIHARA HIDEAKI , KOSHOBU NOBUAKI
IPC分类号： B60R16/02 , B60K37/06 , G05B19/02
摘要： PROBLEM TO BE SOLVED: To provide a system capable of suppressing the increase of man-hours required for program creation of a host controller controlling output devices even when the output devices are variously combined and are used.
SOLUTION: A host 22 transmits output control data in a format defined by relation with a control function thereof. When a controller 21 receives the output control data, the controller 21 transmits the data to display parts 7-9 corresponding to the control function designated by the transmission format.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：即使当输出设备被不同地组合和使用时，提供一种能够抑制控制输出设备的主机控制器的程序创建所需的工时增加的系统。解决方案：主机22以与其控制功能的关系定义的格式发送输出控制数据。当控制器21接收到输出控制数据时，控制器21将数据发送到对应于由传输格式指定的控制功能的显示部分7-9。版权所有（C）2006，JPO＆NCIPI

25. 发明专利

JP2005324644A Input control system, input controller and host controller 审中-公开
标题翻译：输入控制系统，输入控制器和主机控制器
公开(公告)号：JP2005324644A
公开(公告)日：2005-11-24
申请号：JP2004143566
申请日：2004-05-13
申请人： Denso Corp , 株式会社デンソー
发明人： KAMIYA MASAHIRO , NODA SHINICHI , ISHIHARA HIDEAKI , KOSHOBU NOBUAKI
IPC分类号： B60R16/02 , B60K37/06 , B60R16/023 , G06F3/023 , H03M11/04
摘要： PROBLEM TO BE SOLVED: To provide a system capable of suppressing an increase of the man-hour required for preparing a program of an upper rank control device to control an input operation system even when input devices are used in various kinds of combination. SOLUTION: When a switch of a panel 1 is operated, a controller 21 generates the control data corresponding to the control function corresponding to the switch operation based on a design information table 25. When the transmission of the data is requested from a host 22, the control data is read and transmitted to the host 22. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种能够抑制为了控制输入操作系统而控制输入操作系统而准备上级控制装置的程序所需的工时的增加的系统，即使在各种组合中使用输入装置。解决方案：当操作面板1的开关时，控制器21基于设计信息表25产生对应于与开关操作对应的控制功能的控制数据。当从主机22，控制数据被读取并传送给主机22.版权所有：（C）2006，JPO＆NCIPI

26. 发明专利

JP2005114987A Control data output device and control data output method 审中-公开
标题翻译：控制数据输出设备和控制数据输出方法
公开(公告)号：JP2005114987A
公开(公告)日：2005-04-28
申请号：JP2003348431
申请日：2003-10-07
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI
IPC分类号： G09G3/32 , G09G3/20 , H01L33/08 , H01L33/00
摘要： PROBLEM TO BE SOLVED: To provide a control data output device which can output control data for controlling the gray scales of a plurality of loads by using relatively simple circuits without increasing the processing burden by software. SOLUTION: A clock synchronization serial circuit 5 outputs mask data by as much as the number of times set in a mask register 19 in place of a part of the control data within one control period, thereby stopping the display in a LED display element 6 in this period and controlling gray scale lighting of the LED display element 6 arranged with a plurality of LED elements 26 in a matrix form. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种控制数据输出装置，其可以通过使用相对简单的电路输出用于控制多个负载的灰度级的控制数据，而不增加软件的处理负担。解决方案：时钟同步串行电路5在一个控制周期内输出屏蔽寄存器19中设置的次数多于控制数据的一部分的次数，从而停止LED显示中的显示并且控制以矩阵形式布置有多个LED元件26的LED显示元件6的灰度照明。版权所有（C）2005，JPO＆NCIPI

27. 发明专利

JP2004179747A Clamp circuit 有权
公开(公告)号：JP2004179747A
公开(公告)日：2004-06-24
申请号：JP2002340848
申请日：2002-11-25
申请人： Denso Corp , 株式会社デンソー
发明人： NODA SHINICHI , ISHIHARA HIDEAKI
IPC分类号： H03G11/00 , H03K5/007
摘要： PROBLEM TO BE SOLVED: To reduce current consumption in a small power consumption mode. SOLUTION: An analog switch 19 is turned on and an analog switch 20 is turned off in a changeover circuit 18 in an ordinary mode, and output signals from comparators 16, 21 are given to the gates of transistors Q1, Q2. In a standby mode, the analog switch 19 is turned off and the analog switch 20 is turned on, when the functions of terminals 6, 7 are set as analog signal input terminals or digital signal input terminals, voltages VDD-VT, VT are given to the gates of the transistors Q1, Q2, and when the functions of the terminals 6, 7 are set as the digital signal input terminals, voltages VDD and 0V are given to the gates of the transistors Q1, Q2. COPYRIGHT: (C)2004,JPO

28. 发明专利

JP2004048354A Clamp circuit 有权
公开(公告)号：JP2004048354A
公开(公告)日：2004-02-12
申请号：JP2002202680
申请日：2002-07-11
申请人： Denso Corp , 株式会社デンソー
发明人： ABE HIROBUMI , ISHIHARA HIDEAKI , NODA SHINICHI
IPC分类号： H01L27/04 , H01L21/822 , H03K5/08 , H04L25/02 , H04L25/03
CPC分类号： H03K5/08
摘要： PROBLEM TO BE SOLVED: To provide a clamp circuit for decreasing the number of externally mounted components which have been required in prior arts to the utmost and for reducing variations in a clamp voltage due to a temperature change.
SOLUTION: A reference voltage Vr outputted from an operational amplifier 22 is VDD-VGS (Q13). When a voltage Vin1 at a terminal 18 reaches Vr+Vth (Q11) or exceeds it, a transistor Q11 is turned on, and the input voltage Vin1 is clamped at a voltage Vr+VGS (Q11). Since transistors Q11, Q13 are formed to be the same size and thermally coupled closely to each other, the VGS (Q11) stays equal to the VGS (Q13) independently of a temperature change and the clamp voltage VCL is always kept equal to a VDD.
COPYRIGHT: (C)2004,JPO

29. 发明专利

JP2003124811A CLAMP CIRCUIT 审中-公开
公开(公告)号：JP2003124811A
公开(公告)日：2003-04-25
申请号：JP2001316753
申请日：2001-10-15
申请人： DENSO CORP
发明人： ABE HIROBUMI , FUJII HIROSHI , NODA SHINICHI , ISHIHARA HIDEAKI
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8238 , H01L27/092 , H03G11/00 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To decrease necessary external components as much as possible in case of application of a clamp circuit to signal input terminals of an IC. SOLUTION: A comparator 22 has an offset voltage of 0.1 V and compares a terminal voltage Vin1 with a clamp voltage VCL (5.1 V). When the terminal voltage Vin1 is equal to or lower than the clamp voltage VCL, the comparator 22 outputs H and a transistor Q11 is turned off. When a voltage exceeding the clamp voltage VCL is applied as the terminal voltage Vin1 , the comparator 22 outputs L and the transistor Q11 enters a sufficient ON state. At this time, a current flows through an external resistance R11, an input terminal 18, and the transistor Q11 to an output terminal of an operational amplifier 21. This current causes a voltage drop across the resistance R11 and the terminal voltage Vin1 drops down toward the output voltage Vc of the operational amplifier 21.

30. 发明专利

JP2001067235A INTERRUPTION CONTROLLER AND MICROCOMPUTER 失效
公开(公告)号：JP2001067235A
公开(公告)日：2001-03-16
申请号：JP2000152589
申请日：2000-05-24
申请人： DENSO CORP
发明人： MAEDA KOICHI , ISHIHARA HIDEAKI , NODA SHINICHI
IPC分类号： G06F9/46 , G06F9/48 , G06F13/26
摘要： PROBLEM TO BE SOLVED: To obtain an interruption controller capable of using a common CPU regardless of the necessity or unnecessity of multiple interruption and reducing the circuit scale of a CPU by reducing the function of the CPU to the irreducible minimum, and to obtain a microcomputer using the interruption controller. SOLUTION: In this microcomputer capable of multiple interruption, an interruption mask level register 46 which is provided at a CPU 2 side heretofore is provided at an interruption controller 4 side so that the CPU 2 can be miniaturized. The interruption controller 4 is constituted so that an interruption mask level in the interruption mask level register 46 can be saved to an RAM 6 according to a stack signal STK outputted by the CPU 2 simultaneously when the PSR (system register) value and PC(program counter) value of the interruption processing executed until that time are saved to RAM 6 at the time of starting interruption processing, and that the interruption mask level saved to the RAM 6 can be returned to the interruption mask level register 46 according to a return signal RTN outputted by the CPU 2 simultaneously when the PSR value and PC value are read from the RAM 6 at the time of resuming the interrupted interruption processing.

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