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11. 发明专利

JP2007027527A Board and its manufacturing method 审中-公开
标题翻译：董事会及其制造方法
公开(公告)号：JP2007027527A
公开(公告)日：2007-02-01
申请号：JP2005209509
申请日：2005-07-20
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , ARAI SUNAO , MIYASHITA HITOSHI , IIZUKA HAJIME
IPC分类号： H01L23/12 , H01L25/00
摘要： PROBLEM TO BE SOLVED: To provide a board which can increase the positional accuracy of an electronic component fixed to the main body of the board and can make the board thin, and also to provide a method for manufacturing the board.
SOLUTION: The board has a body 11, a recess 21 formed on the board body 11 and nearly corresponding in size to the outer shape of a capacitor component 13, the capacitor component 13 positioned on the recess 21, and notches 22 formed in the board body 11 forming side surfaces of the recess 21.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种能够提高固定在基板主体上的电子部件的位置精度的板，能够使基板变薄，并且还提供一种板的制造方法。解决方案：板具有主体11，形成在板主体11上的几乎对应于电容器部件13的外形几乎相应的凹部21，位于凹部21上的电容器部件13和形成的凹口22 在板体11上形成凹部21的侧表面。版权所有（C）2007，JPO＆INPIT

12. 发明专利

JP2006261246A Wiring circuit board and manufacturing method thereof 有权
标题翻译：接线电路板及其制造方法
公开(公告)号：JP2006261246A
公开(公告)日：2006-09-28
申请号：JP2005073946
申请日：2005-03-15
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： YAMANO KOJI , HARUHARA MASAHIRO , IIZUKA HAJIME , KOYAMA TETSUYA
IPC分类号： H05K1/02 , H01L23/12 , H05K3/46
CPC分类号： H01L23/5383 , H01L21/563 , H01L21/6835 , H01L23/18 , H01L23/3128 , H01L23/49805 , H01L23/49816 , H01L23/5389 , H01L24/81 , H01L25/0655 , H01L2221/68345 , H01L2224/1134 , H01L2224/13144 , H01L2224/136 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81005 , H01L2224/81191 , H01L2224/8121 , H01L2224/81815 , H01L2224/83102 , H01L2224/92125 , H01L2924/00013 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/15192 , H01L2924/15311 , H01L2924/15331 , H01L2924/3511 , H01L2924/381 , H05K1/185 , H05K3/4644 , Y10T29/49126 , Y10T29/4913 , Y10T29/49135 , Y10T29/49155 , Y10T29/49156 , H01L2224/13099 , H01L2924/00 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To realize a thin wiring circuit board comprising a built-in semiconductor chip, and also to control warp of the same wiring circuit board. SOLUTION: The wiring circuit board comprising a built-in semiconductor chip includes an insulating layer for embedding the semiconductor chip and a wiring structure connected to the semiconductor chip. Using the wiring circuit board in which the reinforcing structure to reinforce the insulating layer is embedded to the insulating layer, the thin wiring circuit board is realized, and warp of the board is controlled. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：实现包括内置半导体芯片的薄布线电路板，并且还可以控制同一布线电路板的翘曲。解决方案：包括内置半导体芯片的布线电路板包括用于嵌入半导体芯片的绝缘层和连接到半导体芯片的布线结构。使用其中将加强结构加强绝缘层的布线电路板嵌入到绝缘层中，实现了薄布线电路板，并且控制板的翘曲。版权所有（C）2006，JPO＆NCIPI

13. 发明专利

JP2004200238A Semiconductor device, manufacturing method therefor, method for mounting the same and mounting structure thereof 审中-公开
公开(公告)号：JP2004200238A
公开(公告)日：2004-07-15
申请号：JP2002364155
申请日：2002-12-16
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： IIZUKA HAJIME
IPC分类号： H01L23/28 , H01L21/56 , H01L23/12 , H01L25/065 , H01L25/07 , H01L25/18
CPC分类号： H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device in which an occupying area on a mounting substrate can be reduced, and its manufacturing method and a method for mounting the semiconductor device and a mounting structure.
SOLUTION: The semiconductor device 100 has upper-lower two cut-out semiconductor wafers 5, a resin sealing layer 28 held by these two semiconductor wafers 5 and formed, and conductive posts 30 formed at the outer edge section of the resin sealing layer 28 and exposed to the outside.
COPYRIGHT: (C)2004,JPO&NCIPI

14. 发明专利

JP2003060113A Semiconductor device and method for manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003060113A
公开(公告)日：2003-02-28
申请号：JP2001248052
申请日：2001-08-17
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： HANAGAKI YUJI , IIZUKA HAJIME
IPC分类号： H05K3/46 , H01L23/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, in which a terminal part can be arranged with a spatial margin by securing the arranging area of a terminal part.
SOLUTION: In this semiconductor device 20 mounting a spherical semiconductor element 21 on a substrate 25, the semiconductor element 21 has a plurality of terminal parts 22 formed on its peripheral surface, and is partially or entirely buried in the substrate 25. The substrate 25 has a plurality of layers of wiring patterns 28 laminated via an insulating layer 27, the wiring patterns 28 are connected electrically with the terminal part 22 of the semiconductor element 21 and led out to the surface of the substrate 25 directly or via a via 30. Fixing materials 32 for external connection are formed at the exposed parts of the patterns 28.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种半导体器件，其中端子部分可以通过确保端子部分的布置区域而具有空间裕度来布置。解决方案：半导体元件21在半导体元件21上安装球状半导体元件21，其半导体元件21具有形成于其周面的多个端子部22，部分地或全部被埋设在基板25内。基板25具有经由绝缘层27层叠的多层布线图案28，布线图案28与半导体元件21的端子部分22电连接，并直接或经由通孔30被引出到基板25的表面。固定用于外部连接的材料32形成在图案28的露出部分。

15. 发明专利

JP2009289888A Method of manufacturing substrate with built-in chip 审中-公开
标题翻译：使用内置芯片制造基板的方法
公开(公告)号：JP2009289888A
公开(公告)日：2009-12-10
申请号：JP2008139400
申请日：2008-05-28
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： IIZUKA HAJIME
IPC分类号： H01L23/12 , H05K3/00 , H05K3/34 , H05K3/46
CPC分类号： H01L2224/16225 , H01L2224/73204
摘要： PROBLEM TO BE SOLVED: To solve problems of a conventional method of manufacturing a substrate with a built-in chip by which the completed substrate with the built-in chip is inspected by a continuity test etc. SOLUTION: A first multilayer wiring board 12 and a second multilayer wiring board 52 are formed by a build-up method of laminating a plurality of wiring lines on one surface side of a metal plate with an insulating layer interposed therebetween, and after a through-hole 25 is formed in the first multilayer wiring board 12 so as to enable a semiconductor chip to be mounted through the first multilayer wiring board 12, the first multilayer wiring board 12 and second multilayer wiring board 52 are laminated to form a multilayer substrate. Then it is confirmed through a continuity test that first pads 14 and 54 having exposed both end surfaces are electrically connected through a wiring pattern formed in the multilayer substrate. Then the semiconductor chip is mounted on the second multilayer wiring board 54 through the through-hole 25 of the first multilayer wiring board 12. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：解决现有的利用内置芯片制造衬底的方法的问题，通过该芯片，通过连续性测试等来检查具有内置芯片的完成的衬底。解决方案：A 第一多层布线板12和第二多层布线板52通过在金属板的一个表面侧层压多个布线而形成绝缘层的形成方法，并且在通孔25为形成在第一多层布线板12中，以便能够通过第一多层布线板12安装半导体芯片，层叠第一多层布线板12和第二多层布线板52，以形成多层基板。然后，通过连续性试验证实，具有暴露的两个端面的第一焊盘14和54通过形成在多层基板中的布线图形电连接。然后，半导体芯片通过第一多层布线板12的通孔25安装在第二多层布线板54上。版权所有（C）2010，JPO＆INPIT

16. 发明专利

JP2008311520A Method for manufacturing electronic component built-in substrate 有权
标题翻译：制造电子部件内置衬底的方法
公开(公告)号：JP2008311520A
公开(公告)日：2008-12-25
申请号：JP2007159223
申请日：2007-06-15
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KURASHIMA NOBUYUKI , ARAI SUNAO , IIZUKA HAJIME
IPC分类号： H05K3/46 , H05K1/02 , H05K3/36
CPC分类号： H05K1/144 , H01L21/565 , H01L23/3128 , H01L23/49833 , H01L23/5389 , H01L24/16 , H01L25/105 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/83385 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/3511 , H05K3/284 , H05K2201/09063 , H05K2201/09136 , H05K2201/10674 , H05K2203/1178 , H05K2203/1316 , Y10T29/49126 , Y10T29/4913 , Y10T29/49144 , Y10T29/49165 , Y10T29/49171 , Y10T29/49172 , H01L2924/00 , H01L2224/0401
摘要： PROBLEM TO BE SOLVED: To provide a method for manufacturing an electronic component built-in substrate, which arranges a semiconductor chip between first and second substrates and seals them with resin, and is capable of preventing bubble generation in the resin and effectively preventing curvature in the electronic component and the like. SOLUTION: The method for manufacturing this built-in substrate has a step of mounting a semiconductor chip 110 on a first substrate 100, a step of arranging an underfill resin 109 between the semiconductor chip 110 and the first substrate 100, a step of forming a via hole 206 in the second substrate 200, a step of forming an electrode 112 in the second substrate 200, a step of joining the first substrate 100 and the second substrate 200 so that the semiconductor chip 110 may be built in via the electrode 112, and a step of filling up a sealing resin 115 between the first substrate 100 and the second substrate 200 using a charging pressure that can correct curvature in the semiconductor chip 110 and the first substrate 100, while performing degassing from the via hole 206. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造电子部件内置基板的方法，其将半导体芯片布置在第一和第二基板之间并用树脂密封，并且能够有效地防止树脂中的气泡产生防止电子部件等的弯曲。解决方案：用于制造该内置基板的方法具有将半导体芯片110安装在第一基板100上的步骤，在半导体芯片110和第一基板100之间布置底部填充树脂109的步骤，在第二基板200中形成通孔206，在第二基板200中形成电极112的步骤，将第一基板100和第二基板200接合以使得半导体芯片110可以经由电极112，并且使用可以校正半导体芯片110和第一基板100中的曲率的充电压力在第一基板100和第二基板200之间填充密封树脂115，同时从通孔206进行脱气版权所有（C）2009，JPO＆INPIT

17. 发明专利

JP2005109427A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005109427A
公开(公告)日：2005-04-21
申请号：JP2004054811
申请日：2004-02-27
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： KOBAYASHI TOSHIO , NOSAKA KEIJI , IIZUKA HAJIME , YOSHIHARA TAKAKO
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device for forming a CSP structure at a wafer level which eliminates the need of especially introducing high-cost facilities and improves the production efficiency to reduce the manufacturing cost. SOLUTION: A semiconductor wafer 10 is prepared, having a structure composed of electrodes 20 and an insulation film 18 exposed on the surface. The film 18 is made of a metal-containing resin or a siloxane resin, a seed layer 22 is formed on the insulation layer 18 and the electrodes 20 by electroless plating, a metal film pattern 23 is formed by electroplating utilizing the seed layer 22 as a plating supply layer, the seed layer 22 is etched through the pattern 23 used as a mask, and a wiring pattern 26 connected to the electrodes 20 is formed on the insulation layer 18. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种制造在晶片级形成CSP结构的半导体器件的方法，其不需要特别引入高成本设备并且提高生产效率以降低制造成本。解决方案：制备半导体晶片10，其具有由电极20和暴露在表面上的绝缘膜18构成的结构。膜18由含金属的树脂或硅氧烷树脂制成，通过无电解电镀在绝缘层18和电极20上形成种子层22，通过使用籽晶层22进行电镀而形成金属膜图案23作为电镀供应层，通过用作掩模的图案23蚀刻种子层22，并且在绝缘层18上形成连接到电极20的布线图案26.（C）2005年，JPO和NCIPI

18. 发明专利

JP2013131669A Electronic apparatus and manufacturing method of the same 有权
标题翻译：电子设备及其制造方法
公开(公告)号：JP2013131669A
公开(公告)日：2013-07-04
申请号：JP2011280907
申请日：2011-12-22
申请人： Shinko Electric Ind Co Ltd , 新光電気工業株式会社
发明人： IIZUKA HAJIME
IPC分类号： H01L23/08 , H01L23/02
CPC分类号： H01L31/0203 , H01L21/563 , H01L23/13 , H01L23/49811 , H01L23/49822 , H01L23/49833 , H01L24/16 , H01L25/16 , H01L27/14618 , H01L31/18 , H01L2224/13144 , H01L2224/16225 , H01L2224/16227 , H01L2224/16237 , H01L2224/73204 , H01L2924/00014
摘要： PROBLEM TO BE SOLVED: To prevent a resin from being formed at a part on a lower wiring board and easily form an exposed region in an electronic apparatus having a structure where the resin fills a space between the laminated wiring boards.SOLUTION: An electronic apparatus includes: a first wiring board 3 including a component mounting region A; a second wring board 4 which is laminated on the first wiring board 3, is provided with an opening 4x at a part corresponding to the component mounting region A, and is connected with the first wiring board 3 through solder bumps 50 aligned in a frame like region around the component mounting region A; and a frame like resin dam layer 60 which is formed connecting with an area between the solder bumps 50 around the component mounting region A and encloses the component mounting region A. A sealing resin 64 fills a space between the first wiring board 3 and the second wiring board 4 so that the resin dam layer 60 makes the component mounting region A into a resin non formation region.
摘要翻译：要解决的问题：为了防止在具有树脂填充层叠线路板之间的空间的结构的电子设备中在下布线板的一部分处形成树脂并容易地形成暴露区域。解决方案：电子设备包括：包括部件安装区域A的第一布线板3; 层压在第一布线板3上的第二绞合板4在与部件安装区域A对应的部分处设置有开口4x，并且通过焊接凸块50与第一布线板3连接，区域周围的区域; 以及与构件安装区域A周围的焊料凸块50之间的区域形成的框状的树脂阻挡层60，并且封装有元件安装区域A.密封树脂64填充第一布线基板3与第二布线基板3之间的空间布线板4，使得树脂阻挡层60使部件安装区域A成为树脂非形成区域。

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