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11. 发明专利

JP2004015047A Ferroelectric memory transistor and its manufacturing method 有权
公开(公告)号：JP2004015047A
公开(公告)日：2004-01-15
申请号：JP2003054878
申请日：2003-02-28
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , ZHANG FENGYAN , LI TINGKAI
IPC分类号： H01L27/105 , G11C11/22 , H01L21/28 , H01L21/316 , H01L21/8246 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22 , H01L21/28291 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/11502 , H01L29/78391
摘要： PROBLEM TO BE SOLVED: To provide a non-volatile ferroelectric memory transistor which can prevent the degradation of the memory holding characteristic due to leakage current, and to provide its manufacturing method.
SOLUTION: This ferroelectric memory transistor comprises a substrate including a source region, a gate region and a drain region, a gate stack arranged on the gate region, passivation oxide layers arranged on the substrate and the gate stack, and metallized parts for having each contact with the source/drain regions and the gate stack. The gate stack comprises a High-k insulator element including a first High-k cup and a second High-k cup, a ferroelectric element encapsulated by the High-k insulator element, and an upper electrode arranged on the the High-k insulator element.
COPYRIGHT: (C)2004,JPO

12. 发明专利

JP2003045860A PLASMA ETCHING PROCESS OF Ir-Ta-O ELECTRODE AND CLEANING METHOD AFTER ETCHING 审中-公开
标题翻译： Ir-Ta-O电极的等离子体蚀刻过程和蚀刻后的清洁方法
公开(公告)号：JP2003045860A
公开(公告)日：2003-02-14
申请号：JP2002134738
申请日：2002-05-09
申请人： Sharp Corp , シャープ株式会社
发明人： HON IN , ZHANG FENGYAN , MAA JER-SHEN , SHIEN TEN SUU
IPC分类号： H01L21/3065 , C04B41/53 , C04B41/91 , H01L21/02 , H01L21/3213 , H01L21/8246 , H01L27/105
CPC分类号： H01L21/02071 , C04B41/009 , C04B41/5346 , C04B41/91 , C04B2111/00844 , H01L21/32136 , H01L28/60 , C04B35/495
摘要： PROBLEM TO BE SOLVED: To provide an etching process exhibiting an excellent etching selectivity for removing only an intended material without redepositing the etched substance, and a method for forming an electrode using it.
SOLUTION: The method for forming an electrode in an integrated circuit comprises a step for preparing a silicon based substrate including a step for forming an integrated substrate structure by forming a semiconductor structure on the substrate, a step for depositing an electrode material layer on the substrate structure, and a step for patterning the electrode material layer to form an electrode element wherein the patterning step includes a step for plasma etching the electrode material layer in a plasma reactor of etching gas atmosphere containing a fluorine component.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了提供一种显示出优异的蚀刻选择性的蚀刻工艺，并且不再重新沉积被蚀刻的物质，以及使用该方法形成电极的方法。解决方案：集成电路中形成电极的方法包括制备硅基衬底的步骤，包括通过在衬底上形成半导体结构形成集成衬底结构的步骤，在衬底上沉积电极材料层的步骤结构，以及用于图案化电极材料层以形成电极元件的步骤，其中图案化步骤包括用于在含有氟成分的蚀刻气体气氛的等离子体反应器中等离子体蚀刻电极材料层的步骤。

13. 发明专利

JP2003023140A SINGLE C-AXIS PGO THIN FILM ON ZrO2 FOR NONVOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译： ZrO 2单轴C型轴向PGO薄膜，用于非易失性存储器及其制造方法
公开(公告)号：JP2003023140A
公开(公告)日：2003-01-24
申请号：JP2002084172
申请日：2002-03-25
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , MA YANJUN , MAA JER-SHEN , ZHUANG WEI WEI , SHIEN TEN SUU
IPC分类号： H01L21/02 , H01L21/28 , H01L21/316 , H01L21/8246 , H01L21/8247 , H01L27/105 , H01L29/51 , H01L29/788 , H01L29/792
CPC分类号： H01L21/28291 , H01L21/31604 , H01L21/31691 , H01L28/56 , H01L29/516
摘要： PROBLEM TO BE SOLVED: To realize MFIS transistor structure containing a PGO ferroelectric film. SOLUTION: The MFIS transistor structure is provided with a semiconductor substrate 12 like a silicon substrate, a layer of an insulating film 14 like ZrO2 which is arranged on the semiconductor substrate 12, and a ferroelectric layer 16 which is a single phase (c) axis Pb5 Ge3 O11 (PGO) film arranged on the layer of the insulating film 14. By this structure, superior characteristic can be obtained in high frequency capacitance-voltage(CV) measurement and leakage current (I-V) measurement.
摘要翻译：要解决的问题：实现含有PGO铁电体膜的MFIS晶体管结构。解决方案：MFIS晶体管结构设置有诸如硅衬底的半导体衬底12，布置在半导体衬底12上的诸如ZrO 2的绝缘膜14的层和作为单相（c）轴的铁电层16 Pb5 Ge3O11（PGO）膜，通过这种结构，可以在高频电容电压（CV）测量和漏电流（IV）测量中获得优异的特性。

14. 发明专利

JP2007142386A Photovoltaic structure with conductive nanowire array electrode 审中-公开
标题翻译：具有导电性纳米阵列电极的光伏结构
公开(公告)号：JP2007142386A
公开(公告)日：2007-06-07
申请号：JP2006286176
申请日：2006-10-20
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , BARROWCLIFF ROBERT A , HSU SHENG TENG
IPC分类号： H01L51/42 , H01L31/04
CPC分类号： H01L51/4213 , B82Y10/00 , H01L51/0046 , H01L51/0048 , H01L51/4226 , H01L51/4233 , H01L51/441 , Y02E10/52 , Y02E10/549
摘要： PROBLEM TO BE SOLVED: To provide an inexpensive photovoltaic structure, for a photovoltaic device using a conductive nanowire array electrode.
SOLUTION: A photovoltaic (PV) structure provided with a conductive nanowire array electrode is provided, comprising the steps of forming a conductive nanowire 104 on a bottom electrode 102; forming a first semiconductor layer 106 of a first dopant type placed on the nanowire 104; forming a second semiconductor layer 108 of a second dopant type opposite to the first dopant type; and forming a top electrode 110 placed on the second semiconductor layer 108. The first and second semiconductor layers 106 and 108 can be made of materials such as a conductive polymer, a conjugated polymer having a fullerene derivative or an inorganic material including CdSe, CdS, titania, or ZnO. The conductive nanowire 104 can be made of materials such as IrO
2 , In
2 O
3 , SnO
2 , or an indium tin oxide (ITO).
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：为了提供廉价的光伏结构，对于使用导电纳米线阵列电极的光伏器件。提供了一种设置有导电纳米线阵列电极的光伏（PV）结构，包括在底部电极102上形成导电纳米线104的步骤; 形成放置在纳米线104上的第一掺杂剂类型的第一半导体层106; 形成与第一掺杂剂类型相反的第二掺杂剂类型的第二半导体层108; 并且形成放置在第二半导体层108上的顶部电极110.第一和第二半导体层106和108可以由诸如导电聚合物，具有富勒烯衍生物的共轭聚合物或包括CdSe，CdS，二氧化钛或ZnO。导电纳米线104可以由诸如IrO 2 SBS，SnO 2，SBO 2，SBO 2，SBO 2，或氧化铟锡（ITO）。版权所有（C）2007，JPO＆INPIT

15. 发明专利

JP2007067404A Method of etching top electrode/ferroelectric stack film 审中-公开
标题翻译：蚀刻顶电极/电解堆叠薄膜的方法
公开(公告)号：JP2007067404A
公开(公告)日：2007-03-15
申请号：JP2006230589
申请日：2006-08-28
申请人： Sharp Corp , シャープ株式会社
发明人： ULRICH BRUCE D , STECKER LISA H , ZHANG FENGYAN , HSU SHENG TENG
IPC分类号： H01L21/8246 , H01L21/3065 , H01L21/822 , H01L27/04 , H01L27/105
CPC分类号： H01L28/55 , H01L21/31122
摘要： PROBLEM TO BE SOLVED: To provide a method of etching a top electrode/ferroelectric stack film. SOLUTION: The method of etching a top electrode/ferroelectric stack film comprises: a step of forming a first layer of a first dielectric material on a substrate; a step of forming a bottom electrode in the first layer of a first dielectric material; a step of depositing an etch stop layer on the first layer of a first dielectric material and the bottom electrode, and forming an opening therein; a step of depositing a layer of a ferroelectric material; a step of depositing a top electrode material on the layer of a ferroelectric material to form a top electrode/ferroelectric material stack film and stack-etching the top electrode and the layer of a ferroelectric material; a step of depositing a second layer of a second dielectric material and sealing the top electrode and ferroelectric material; a step of etching the second layer of a second dielectric material and forming a sidewall around the top electrode and ferroelectric material; a step of depositing a second layer of the first dielectric material; and a step of depositing second and third layers of the first dielectric material. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种蚀刻顶部电极/铁电堆叠膜的方法。蚀刻顶部电极/铁电堆叠膜的方法包括：在衬底上形成第一电介质材料的第一层的步骤; 在第一电介质材料的第一层中形成底电极的步骤; 在第一介电材料和底电极的第一层上沉积蚀刻停止层并在其中形成开口的步骤; 沉积铁电材料层的步骤; 将上电极材料沉积在铁电材料层上以形成顶电极/铁电材料堆叠膜并叠层蚀刻顶电极和铁电材料层的步骤; 沉积第二电介质材料的第二层并密封顶电极和铁电材料的步骤; 蚀刻第二电介质材料的第二层并围绕顶电极和铁电材料形成侧壁的步骤; 沉积第一介电材料的第二层的步骤; 以及沉积第一和第三层第一介电材料的步骤。版权所有（C）2007，JPO＆INPIT

16. 发明专利

JP2006228722A Electroluminescent device, method for manufacturing the electroluminescent device, and light emission method with the electroluminescent device 审中-公开
标题翻译：电致发光器件，制造电致发光器件的方法和具有电致发光器件的光发射方法
公开(公告)号：JP2006228722A
公开(公告)日：2006-08-31
申请号：JP2006025117
申请日：2006-02-01
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , ZHANG FENGYAN , STECKER GREGORY M , BARROWCLIFF ROBERT A
IPC分类号： H05B33/26 , H05B33/10 , H05B33/14 , H05B33/28
CPC分类号： H05B33/145
摘要： PROBLEM TO BE SOLVED: To realize an electroluminescent device of low output power, which can generate high electric field, using low voltage supply.
SOLUTION: The electroluminescent device has a pair of electrodes comprising an upper electrode 102 and a lower electrode 108 between which a silicon phosphor layer 106 including a phosphor is formed, where the lower electrode 102 has a nanostructure, in which a plurality of micro-protrusions 104 in the order of nanometers are formed, and the silicon phosphor layer 106 is formed so as to cover the micro-protrusions 104.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：使用低电压电源实现可产生高电场的低输出功率的电致发光器件。电致发光器件具有包括上电极102和下电极108的一对电极，在该电极102和下电极108之间形成有包含磷光体的磷光体层106，其中下电极102具有纳米结构，其中多个形成大约数量级的微突起104，并且形成硅磷光体层106以覆盖微突起104.（C）2006年，JPO和NCIPI

17. 发明专利

JP2006117520A Iridium oxide nanotube and method of forming the same 审中-公开
标题翻译：氧化镍纳米管及其形成方法
公开(公告)号：JP2006117520A
公开(公告)日：2006-05-11
申请号：JP2005300934
申请日：2005-10-14
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , BARROWCLIFF ROBERT A , GREGORY M STECKER , HSU SHENG TENG
IPC分类号： C01G55/00 , B82B1/00 , B82B3/00 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L23/52
CPC分类号： B82Y10/00 , B82Y30/00 , C30B25/00 , C30B29/16 , C30B29/605 , Y10S977/811 , Y10S977/84
摘要： PROBLEM TO BE SOLVED: To provide a method of forming an iridium oxide (IrOx) nanotube without using a template.
SOLUTION: The method comprises: providing a substrate; introducing a (methyl cyclopentadienyl)(1,5-cyclooctadiene) iridium (1) precursor; introducing oxygen as a precursor reaction gas; establishing final pressure in the range of 1 Torr to 50 Torr; and growing the IrOx hollow nanotube from the surface of the substrate with the use of metalorganic chemical vapor deposition method (MOCVD). Representatively, the (methyl cyclopentadienyl)(1,5-cyclooctadiene)iridium (1) precursor is initially heated to a 1st temperature within the range of 60°C to 90°C in an ampule and kept at the 1st temperature in a transporting line for introducing the precursor. The precursor can be mixed with an inert carrier gas such as Ar or oxygen which is the precursor reaction gas can be used as the carrier gas.
COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：待解决的问题：提供在不使用模板的情况下形成氧化铱（IrOx）纳米管的方法。解决方案：该方法包括：提供衬底; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（1）前体; 引入氧气作为前体反应气体; 确定1 Torr至50 Torr范围内的最终压力; 并使用金属有机化学气相沉积法（MOCVD）从衬底的表面生长IrOx中空纳米管。代表性地，（甲基环戊二烯基）（1,5-环辛二烯）铱（1）前体最初在安瓿中加热至60℃至90℃范围内的第一温度，并在传输线中保持在第一温度用于引入前体。前体可以与诸如Ar或氧的惰性载气混合，其中前体反应气体可以用作载气。版权所有（C）2006，JPO＆NCIPI

18. 发明专利

JP2005175461A Asymmetrical area memory cell 审中-公开
标题翻译：不对称区域记忆细胞
公开(公告)号：JP2005175461A
公开(公告)日：2005-06-30
申请号：JP2004335193
申请日：2004-11-18
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , ZHANG FENGYAN
IPC分类号： H01L21/28 , G11C11/15 , G11C13/00 , H01L21/3205 , H01L21/8239 , H01L21/8246 , H01L23/52 , H01L27/105 , H01L27/115 , H01L27/22 , H01L27/24 , H01L29/68 , H01L43/08 , H01L45/00
CPC分类号： H01L27/105 , G11C13/0007 , G11C2213/31 , G11C2213/52 , H01L27/1052 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide an asymmetrical area memory cell and a method of manufacturing the same. SOLUTION: The method of manufacturing the asymmetrical area memory cell includes a step of forming a lower electrode 102 having a certain area, a step of forming a CMR memory film 106 having an asymmetrical area on the lower electrode, and a step of forming an upper electrode 110 having an area narrower than the lower electrode area. In a certain aspect, the CMR film has a first area adjacent to the upper electrode, and a second area adjacent to the lower electrode and larger than the first area. Representatively, the first area of the CMR film is substantially equal to the upper electrode area, but the second area of the CMR film can become narrower than the lower electrode area. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供一种非对称区域存储单元及其制造方法。解决方案：制造不对称区域存储单元的方法包括形成具有一定面积的下电极102的步骤，在下电极上形成具有不对称区域的CMR存储膜106的步骤，以及步骤形成具有比下电极区域窄的区域的上电极110。在某一方面，CMR膜具有与上电极相邻的第一区域和与下电极相邻并且大于第一区域的第二区域。代表性地，CMR膜的第一区域基本上等于上电极区域，但是CMR膜的第二区域可以变得比下电极区域窄。版权所有（C）2005，JPO＆NCIPI

19. 发明专利

JP2005175457A Rram memory cell electrode 审中-公开
标题翻译： RRAM记忆体电极
公开(公告)号：JP2005175457A
公开(公告)日：2005-06-30
申请号：JP2004332503
申请日：2004-11-16
申请人： Sharp Corp , シャープ株式会社
发明人： SHIEN TEN SUU , PAN WEI , ZHANG FENGYAN , ZHUANG WEI-WEI , LI TINGKAI
IPC分类号： H01L21/28 , G11C13/00 , G11C16/02 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L27/22 , H01L29/68 , H01L39/00 , H01L43/08 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide an electrode which can be formed economically and which is reliable to improve the reliability of a device and the durability of the device.
SOLUTION: An RRAM memory cell includes a first oxidation resistance layer 20, a first heat resistance metal layer 22, a CMR layer 24, a second heat-resistant metal layer 26, and a second oxidation resistance layer 28; and is formed on a silicon substrate having a metal plug 16 which is connected operably in the silicon substrate, and which is formed on the silicon substrate. For example, the oxide resistance layer is formed of a material obtained from the group of the materials constituted of TiN, TaN, TiAlN
x , TaAlN
x , TaSiN, TiSiN and RuTiN.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：解决的问题：提供可以经济地形成并且可靠地提高装置的可靠性和装置的耐久性的电极。解决方案：RRAM存储单元包括第一抗氧化层20，第一耐热金属层22，CMR层24，第二耐热金属层26和第二抗氧化层28; 并且形成在具有可操作地连接在硅衬底中并且形成在硅衬底上的金属插塞16的硅衬底上。例如，氧化物电阻层由从由TiN，TaN，TiAlN，SBA，TiAlN，TiSiN和RuTiN构成的材料组得到的材料形成。版权所有（C）2005，JPO＆NCIPI

20. 发明专利

JP2005109446A Etching process of single mask pt/pcmo/pt stack to be applied to rram 有权
标题翻译：单掩模PT / PCMO / PT堆栈的蚀刻过程应用于RRAM
公开(公告)号：JP2005109446A
公开(公告)日：2005-04-21
申请号：JP2004247537
申请日：2004-08-26
申请人： Sharp Corp , シャープ株式会社
发明人： ZHANG FENGYAN , SHIEN TEN SUU
IPC分类号： H01L21/28 , G11C13/00 , H01L21/02 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , H01L21/31122 , H01L21/32136 , H01L27/101 , H01L28/55 , H01L28/65 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1675
摘要： PROBLEM TO BE SOLVED: To provide a method for dry etching of a Pt/PCMO(Pr
1-x Ca
x MnO
3 )/Pt stack.
SOLUTION: The method for dry etching of the PCMO stack includes a step in which a substrate is prepared, a step in which a barrier layer is deposited, a step in which an under electrode is deposited, a step in which a PCMO thin film is deposited, a step in which an upper electrode is deposited, a step in which a hard mask layer is deposited, a step in which photoresist is applied to and patterning is carried out, a step in which the hard mask layer is etched, a step in which dry etching carrying out of the upper electrode, a step in which dry etching carrying out of the PCMO layer consisting of plural step etching processes, a step in which dry etching carrying out of the under electrode, and a step in which a device having a PCMO base is completed.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种用于干法蚀刻Pt / PCMO（Pr 1-x xS MnO 3 SB / ）/ Pt堆叠。解决方案：用于干法蚀刻PCMO堆叠的方法包括其中准备衬底的步骤，其中沉积阻挡层的步骤，沉积下电极的步骤，其中PCMO 沉积薄膜，沉积上电极的步骤，其中沉积硬掩模层的步骤，其中施加光致抗蚀剂并进行图案化的步骤，其中硬掩模层被蚀刻的步骤，进行上述电极的干蚀刻的步骤，进行由多个阶梯蚀刻工艺组成的PCMO层的干蚀刻的步骤，进行下部电极的干蚀刻的步骤，以及已经完成了具有PCMO基座的装置。版权所有（C）2005，JPO＆NCIPI

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