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11. 发明专利

JPH10161689A SURROUND CIRCUIT 失效
公开(公告)号：JPH10161689A
公开(公告)日：1998-06-19
申请号：JP32035896
申请日：1996-11-29
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H04S1/00 , G10K15/12
摘要： PROBLEM TO BE SOLVED: To reduce the number of D/A converting circuit in a surround circuit using an A/D converting circuit, a delay circuit and a D/A converting circuit. SOLUTION: The input signal of an input terminal IN is converted into a digital signal in an A/D converting circuit 11, and delayed by a memory 12. The output signal of the memory 12 is converted into an analog signal in a D/A converting circuit 13. The sampling frequency of the A/D converting circuit 11 is fixed, while the sampling frequency of the D/A converting circuit 13 is changed in time. Therefore, the sampling frequencies of the A/D converting circuit 11 and the D/A converting circuit 13 to the same digital signal are mutually differed, the frequency of the output signal of the D/A converting circuit 13 is differed from the frequency of the input signal of the A/D converting circuit 11, and the frequency of the input signal can be thus dispersed to various frequencies.

12. 发明专利

JPH0738441A A/D CONVERTER 失效
公开(公告)号：JPH0738441A
公开(公告)日：1995-02-07
申请号：JP17951493
申请日：1993-07-21
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： G10K15/12 , H03M3/02
摘要： PURPOSE:To revise a time constant of a variable integration circuit. CONSTITUTION:The A/D converter receives a pulse signal representing up-down of a time constant, counts the signal and provides a revision signal of time constant by count-up. In the case of up-count, a flip-flop circuit 8 for each bit is forcibly set to 1 by an L level of an input signal. Thus, the circuits 80 act as an up counter of high order 2-bits (control bits). Then the time constant is revised quickly by revising the time constant of a variable integration circuit by the output of the high order 2-bits. On the other hand, when the input signal is logical H, the circuits 80 act as a 5-bit down-counter. Then the time constant of the variable integration circuit is slowly revised.

13. 发明专利

JPH0736473A STORAGE CIRCUIT 失效
公开(公告)号：JPH0736473A
公开(公告)日：1995-02-07
申请号：JP17951693
申请日：1993-07-21
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： G10K15/12 , G11C27/00
摘要： PURPOSE:To access plural addresses of a memory at the same time. CONSTITUTION:A controller 32 controls whether address counters 34 and 35 are used as one counter or as two individual counters. Namely, when the address counters are used as one counter, a memory 31 is accessed after the memory 30 is accessed and when they are used as two counters, two addresses are accessed with the outputs of the two address counters 34 and 35. Consequently, the memories 30 and 31 can be utilized by being switched to one memory or two memories at need.

14. 发明专利

JPH03132300A CONTROL CIRCUIT FOR NOISE SEQUENCER 失效
公开(公告)号：JPH03132300A
公开(公告)日：1991-06-05
申请号：JP27061989
申请日：1989-10-18
申请人： SANYO ELECTRIC CO
发明人： MEYA MASATO
IPC分类号： H04S7/00
摘要： PURPOSE:To obtain a test signal of 4 and 3 channels by using an output signal of a D-FF to reset an input buffer thereby obtaining a control signal from an output terminal of an output buffer circuit. CONSTITUTION:An output buffer circuit 11 comprising 3rd - 6th D-FF 7 - 10, which outputs an output signal of a decode circuit 6 decoding an output signal of an input buffer circuit 5 comprising 1st and 2nd D-FF 3,4 in response to a 1st frequency divider output signal Q1 of a frequency divider circuit 2. Moreover, a D-FF 14 is provided, which resets an input buffer circuit 2 in response to a 2nd frequency divider output signal Q2 of the frequency divider circuit 2 and an output signal of a NAND gate 13 receiving an output signal of the input buffer circuit 5 and an output control signal of the switch 12. Then the output signal of the D-FF is used to reset the input buffer circuit 5 and a control signal driving a noise sequencer is obtained from an output terminal of the output buffer circuit 11. Thus, a test signal of 4 and 3-channels is generated.

15. 发明专利

JP2011009989A Sample hold circuit 审中-公开
标题翻译：样品保持电路
公开(公告)号：JP2011009989A
公开(公告)日：2011-01-13
申请号：JP2009150719
申请日：2009-06-25
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , KIMURA YASUYUKI , SERIZAWA SHUNSUKE
IPC分类号： H03F3/70 , G11C27/02
摘要： PROBLEM TO BE SOLVED: To solve such a problem that an offset potential voltage of an output signal is easy to vary in a sample hold circuit having an inverting amplifier circuit configured of a CMOS inverter.SOLUTION: A CMOS inverter circuit 14 provided on the output stage of a sample hold circuit 2 includes: a PMOS transistor Mand an NMOS transistor Mhaving a common signal input to the respective gates; an NMOS transistor Mwhich is diode-connected between the Mand a positive voltage source V; and a PMOS transistor Mwhich is diode-connected between the Mand a ground potential GND.
摘要翻译：要解决的问题：为了解决在具有由CMOS反相器构成的反相放大器电路的采样保持电路中输出信号的偏移电位电压容易变化的问题。解决方案：设置在输出端的CMOS反相器电路14 采样保持电路2的阶段包括：PMOS晶体管Mand，NMOS晶体管M输入输入到各个门的公共信号; 一个NMOS晶体管M，二极管连接在Mand一个正电压源V之间; 以及在Mand地电位GND之间二极管连接的PMOS晶体管M。

16. 发明专利

JP2010251876A Switched capacitor filter circuit 审中-公开
标题翻译：开关电容滤波电路
公开(公告)号：JP2010251876A
公开(公告)日：2010-11-04
申请号：JP2009096670
申请日：2009-04-13
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： MEYA MASATO , SERIZAWA SHUNSUKE
IPC分类号： H03H19/00 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To solve a problem wherein offset voltage potential is tended to change for of an output signal of a switched capacitor filter (SCF) circuit, which constitutes an inverting amplifier circuit by an inverter.
SOLUTION: The SCF circuit 2 includes two SCFs 4 and 6 equipped with inverter circuits 14a and 14b at the output stage, and generates a differential type output signal. Resistors R
A and R
B , connected between differential output terminals, divides the voltage of differential signal to generate middle point potential voltage V
CM . A comparator 30 compares the V
CM with target potential voltage V
CT . A transistor connected between a CMOS inverter of the inverter circuits 14a and 14b and ground potential changes channel resistance according to the comparison results at the comparator 30, changes bias potential voltage of the output end of the CMOS inverter, and carries out feedback control for feeding the offset potential voltage towards the V
CT .
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：解决的问题：为了解决由逆变器构成反相放大器电路的开关电容滤波器（SCF）电路的输出信号的偏移电压电位倾向于变化的问题。解决方案：SCF电路2包括在输出级配备有反相器电路14a和14b的两个SCF 4和6，并产生差分型输出信号。连接在差分输出端子之间的电阻器R A 和R B 将差动信号的电压分频，产生中点电位电压V SB。比较器30将V CM 与目标电位电压V 进行比较。连接在反相器电路14a和14b的CMOS反相器之间的晶体管和接地电位根据比较器30的比较结果改变沟道电阻，改变CMOS反相器的输出端的偏置电位电压，并且执行用于馈送的反馈控制朝向V 的偏移电位电压。版权所有（C）2011，JPO＆INPIT

17. 发明专利

JP2009111865A Color signal processing circuit 审中-公开
标题翻译：彩色信号处理电路
公开(公告)号：JP2009111865A
公开(公告)日：2009-05-21
申请号：JP2007283889
申请日：2007-10-31
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： NIKI MASA , MEYA MASATO
IPC分类号： H04N9/64
摘要： PROBLEM TO BE SOLVED: To provide a color signal processing circuit which effectively detects a pedestal level voltage.
SOLUTION: First and second capacitors 22, 24 are supplied with demodulated first color signals on either even-numbered or odd-numbered horizontal lines only during an ID signal term of the demodulated first color signal, and the demodulated first color signal are charged to an ID signal voltage of the first color signals. Third and fourth capacitors 26, 28 are supplied with charges of the first and second capacitors 22, 24 multiple times during a term other than the ID signal term, thereby being charged to the ID signal voltage of the first color signals or an ID signal voltage of second color signals. In accordance with the voltage of the third and fourth capacitors 26, 28, a pedestal level voltage of the first and second color signals is obtained.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供有效地检测基座电平电压的彩色信号处理电路。解决方案：第一和第二电容器22,24仅在解调的第一颜色信号的ID信号项期间在偶数或奇数水平线上被提供解调的第一颜色信号，并且解调的第一颜色信号是充电到第一颜色信号的ID信号电压。第三和第四电容器26,28在ID信号项以外的期间多次被提供给第一和第二电容器22,24的电荷，从而被充电到第一颜色信号的ID信号电压或ID信号电压的第二色信号。根据第三和第四电容器26,28的电压，获得第一和第二颜色信号的基座电平电压。版权所有（C）2009，JPO＆INPIT

18. 发明专利

JP2009055525A Analog memory circuit and video signal processing circuit 审中-公开
标题翻译：模拟记忆电路和视频信号处理电路
公开(公告)号：JP2009055525A
公开(公告)日：2009-03-12
申请号：JP2007222432
申请日：2007-08-29
申请人： Sanyo Electric Co Ltd , Sanyo Semiconductor Co Ltd , 三洋半導体株式会社 , 三洋電機株式会社
发明人： SERIZAWA SHUNSUKE , MEYA MASATO
IPC分类号： H04N9/78
摘要： PROBLEM TO BE SOLVED: To precisely hold electric charges that correspond to the signal level of an input signal.
SOLUTION: An analog memory circuit includes a capacitor for holding electric charges that correspond to the signal level of an input signal, an input circuit for inputting the input signal to one end of the capacitor in the case the input control signal for controlling input of the electric charges is at one of the logic levels which directs input of the electric charges, an output circuit for outputting the electric charges accumulated in the capacitor in the case the output control signal for controlling output of electric charges is at the one of the logic levels which directs output of the electric charges, and an electric charge holding circuit for applying a voltage of a predetermined level to the other end of the capacitor in the case the output control signal is at the other of the logic levels.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：精确地保持与输入信号的信号电平对应的电荷。解决方案：模拟存储器电路包括用于保持与输入信号的信号电平相对应的电荷的电容器，用于在用于控制的输入控制信号的情况下将输入信号输入到电容器的一端的输入电路电荷的输入处于引导电荷输入的逻辑电平之一，输出电路，用于在控制电荷输出的输出控制信号处于电容的输出的情况下输出累积在电容器中的电荷指示电荷输出的逻辑电平，以及在输出控制信号处于逻辑电平的另一个的情况下，向电容器的另一端施加预定电平的电压的电荷保持电路。版权所有（C）2009，JPO＆INPIT

19. 发明专利

JP2007097019A Delay circuit and video signal processing circuit employing same 审中-公开
标题翻译：延迟电路和使用其的视频信号处理电路
公开(公告)号：JP2007097019A
公开(公告)日：2007-04-12
申请号：JP2005286081
申请日：2005-09-30
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： SERIZAWA SHUNSUKE , SAKATA TETSUO , MEYA MASATO
IPC分类号： H04N9/64 , H03H11/26
CPC分类号： H03H19/004 , H04N11/165 , H04N11/186
摘要： PROBLEM TO BE SOLVED: To provide a delay circuit utilizing a switched/capacitor for decreasing a parasitic capacitance between a drain and a substrate, and to provide a video signal processing circuit employing the delay circuit. SOLUTION: The delay circuit includes: a switched-capacitor group including a plurality of switched-capacitor sections each including charging/discharging transistors and a capacitive element connected to the sources of the transistors wherein an input signal is given to each of the drains of the charging transistors in common and the charging transistors are connected to charge the capacitive elements, the discharging transistors are connected to discharge the capacitive elements from each of the drains and to output an output signal; and a switching control section that controls ON/OFF of the gates of the charging/discharging transistors to sequentially charge the capacitive elements on the basis of the input signal and to sequentially output the output signal by discharging the capacitive element having previously been charged in the sequential charging, and in the two switched-capacitor sections adjacent to each other, both the charging/discharging transistors are arranged adjacent to each other and the drains of both the charging/discharging transistors are connected in common. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供利用开关电容器的延迟电路，用于减小漏极和衬底之间的寄生电容，并提供采用延迟电路的视频信号处理电路。解决方案：延迟电路包括：开关电容器组，包括多个开关电容器部分，每个开关电容器部分包括充电/放电晶体管和连接到晶体管的源极的电容元件，其中输入信号被提供给连接充电晶体管的漏极和充电晶体管连接以对电容元件充电，放电晶体管被连接以从每个漏极放电电容元件并输出输出信号; 以及开关控制部，其控制充电/放电晶体管的栅极的接通/断开，以基于输入信号对电容元件顺序充电，并且通过将先前已被充电的电容元件放电来顺序地输出输出信号顺序充电，并且在彼此相邻的两个开关电容器部分中，两个充电/放电晶体管彼此相邻布置，并且两个充电/放电晶体管的漏极相连。版权所有（C）2007，JPO＆INPIT

20. 发明专利

JP2007036872A Analog memory circuit and video signal processing apparatus 审中-公开
标题翻译：模拟记忆电路和视讯信号处理装置
公开(公告)号：JP2007036872A
公开(公告)日：2007-02-08
申请号：JP2005219374
申请日：2005-07-28
申请人： Sanyo Electric Co Ltd , 三洋電機株式会社
发明人： MEYA MASATO
IPC分类号： H04N9/78 , H01L23/12 , H01L23/14
摘要： PROBLEM TO BE SOLVED: To provide an analog memory circuit suitable for processing a high-frequency signal, such as video signal.
SOLUTION: The aforementioned problem can be solved by the analog memory circuit 42 that includes a memory unit 52 provided with a capacitor C for maintaining a sampled input signal as electric charges; and also provided with switching elements Tia, Tib, Toa and Tob for switching between a first mode for supplying the input signal to the capacitor C, during sampling to cause the capacitor C to accumulate electric charges corresponding to the intensity of the input signal, and a second mode for connecting both ends of the capacitor C to an inversion output terminal and an output terminal of an operational amplifier at the time of output.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供适合于处理诸如视频信号的高频信号的模拟存储器电路。解决方案：上述问题可以通过模拟存储器电路42来解决，模拟存储器电路42包括：具有电容器C的存储单元52，用于将采样输入信号保持为电荷; 并且还在开关元件Tia，Tib，Toa和Tob之间切换，以便在采样期间在用于向电容器C提供输入信号的第一模式之间切换，以使电容器C累积对应于输入信号的强度的电荷，以及用于将电容器C的两端连接到输出时的运算放大器的反转输出端子和输出端子的第二模式。版权所有（C）2007，JPO＆INPIT

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