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    • 11. 发明专利
    • GROUNDDFAULT DETECTING CIRCUIT
    • JPS5637762A
    • 1981-04-11
    • JP11280579
    • 1979-09-05
    • HITACHI LTDNIPPON TELEGRAPH & TELEPHONE
    • KITANO JIYUNJIROUTAKESHITA TETSUOOIKAWA YOSHINORI
    • H04M3/22H02H3/32H04M3/30H04Q3/72
    • PURPOSE:To obtain a ground-fault detecting circuit suited for formation of the semiconductor integrated circuit, by generating the voltage proportional to the battery line current based on the reference voltage set previously and then comparing the voltage with the voltage proportional to the ground current. CONSTITUTION:When the hook switch of the telephone TEL is turned on, the loop current flows from the ground G' and via the ground line B, TEL, battery line A and battery VBB each. And if the line A has a ground-fault with the resistance RG' due to occurrence of the fault, the ground current flows in addition to the loop current. And thus the battery line current IA becomes larger than the ground line current IB. The current/voltage converting circuit consisting of the transistor TrQ0 and resistances R10 plus R11 generates the voltage proportional to the current IA via the base of the TrQ1 and based on the reference power source VREF. And the voltage proportional to the current IB is generated at the base of the TrQ2 via the resistance R10'. The TrQ1 and Q2 from the voltage comparator. And when the current IA becomes larger than the current IB by the source VREF and by an amount equivalent to the current value set previously, the TrQ1 is turned on to give an inversion to the output of the voltage comparator. Thus the ground-fault detection is carried out.
    • 17. 发明专利
    • NETWORK DRIVING SYSTEM
    • JPS54116812A
    • 1979-09-11
    • JP2345878
    • 1978-03-03
    • HITACHI LTDNIPPON TELEGRAPH & TELEPHONE
    • MUKAEMACHI TAKUJITAKESHITA TETSUOSHIMIZU KIICHIHIMENO RIYOUICHI
    • H04Q3/52
    • PURPOSE:To improve noise proof with the size and the number of driving lines both reduced by selectively driving switches by sending out each assignment information in a time-division mode corresponding stages in a network with semiconductor channel switches of multi-layer structure arrayed in a matrix shape. CONSTITUTION:Switch controller 100 is provided which is connected to a controller, as to the driving control of a network of multi-stage structure using switch matrixes 1 to 10 obtained by arraying, in a matrix shaped, semiconductor channel switches of PNPN four-layer structure controlled by more than three input pieces of information. This controller 100 is equipped with register 101 receiving control information, timing circuit 102 generating various timing pulses needed for the switch control, information expansion decoders 103 to 106, current absorbing circuits 107 to 109 for fan-out buffer assignment, and driving current supply circuits 110 and 111; respective pieces of assignment information inputted to register 101 are sent out in the time-division mode corresponding to stages so as to drive selectively a desirable switch in each stage.