专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

12. 发明专利

JPS57152230A LOGICAL GATE CIRCUIT 失效
公开(公告)号：JPS57152230A
公开(公告)日：1982-09-20
申请号：JP3697581
申请日：1981-03-13
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K19/088 , H03K19/003 , H03K19/20
摘要： PURPOSE:To prevent malfunction and to reduce power consumption by providing a diode whose anode and cathode are connected to the emitter of the 1st PNP transistor (TR) of an inverter circuit and to that of the 2nd PNPTR of an NAND circuit. CONSTITUTION:An inverter TRQ1 receives the 1st input signal, and an inverter TRQ4 receives the 2nd input signal. An output signal from the TRQ1 is sent to an emitter follower TRQ2, and while a diode D8 is connected between the output of the TRQ1 and that of the TRQ4, the emitter output terminal of the TRQ2 is grounded through a diode D7. This diode D7 shifts the threshold level of an inverter circuit 10, and the diode D8 inhibits a current flowing through the resistance R1 of the circuit 10 from flowing to a terminal 2 through the diode D5 of an NAND circuit 20 when the input terminals 1 and 2 are at a high and a low potential respectively.

14. 发明专利

JPS58104532A SATURATED TYPE LOGICAL CIRCUIT 失效
公开(公告)号：JPS58104532A
公开(公告)日：1983-06-22
申请号：JP20285181
申请日：1981-12-16
申请人： NIPPON ELECTRIC CO
发明人： KIYOZUKA NOBORU , MORI SUSUMU
IPC分类号： H03K19/088 , H03K19/013
摘要： PURPOSE:To attain high-speed operation of a saturated type logical circuit, by improving an active pull-down circuit. CONSTITUTION:A saturated logical circuit is formed with a PNP input transistor (TR)Q1 connected to a power supply via an emitter resistor R1, a level shift TRQ2, a phase split stage TRQ3, and a common emitter output TRQ4. The emitter of TRQ7 the base of which is connected to the collector of the level shift TRQ2 via a resistor R3, is grounded, the collector is connected to the base of the output TRQ4 via a resistor R8, and the anode and cathode of a diode D2 are connected between the base of the TRQ7 and the collector of the PNP input TRQ1, and the collector of the PNP input TRQ1 is grounded via a resistor R4. The collector potential of the level shift TRQ2 is detected, allowing to interrupt/ conduct the TRQ7 in conducting/interrupting the output TRQ4.

15. 发明专利

JPS57188138A LOGICAL GATE CIRCUIT 失效
公开(公告)号：JPS57188138A
公开(公告)日：1982-11-19
申请号：JP7291181
申请日：1981-05-15
申请人： NIPPON ELECTRIC CO , NIPPON ELECTRIC IC MICROCOMPUT
发明人： MORI SUSUMU , YAMADA HIDEAKI
IPC分类号： H03K19/00 , H03K19/013 , H03K19/088 , H03K19/20
摘要： PURPOSE:To reduce the difference in transmission delay time from two input terminals, by connecting an inverter transistor (TR) receiving the 2nd input to an output of an inverter transistor receiving the 1st input, in a TTL having the NAND function of the 1st input NOT signal and the 2nd input. CONSTITUTION:The 1st input signal is inputted to an inverter circuit 10 consisting of TRs Q1 and Q2 and the signal is applied to the intermediate stage TRQ5 from the collector of the TRQ2 with inversion. The 2nd input signal is also applied to an input RRQ4 and applied to the TRQ5 from the collector via a level shift diode D4. The 2nd input signal is applied to a PNP TRQ10, the emitter is connected to the collector of the TRQ1 to flow a current flowing a resistor R1 to a ground terminal via a TRQ10 when the 1st input is at H and the 2nd input is at L.

16. 发明专利

JPS5642434A LOGIC GATE CIRCUIT 失效
公开(公告)号：JPS5642434A
公开(公告)日：1981-04-20
申请号：JP11819679
申请日：1979-09-14
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K19/088
摘要： PURPOSE:To make it possible to improve output dielectric strength greatly by providing a pulldown transistor. CONSTITUTION:Pulldown transistor TRQ7 is provided. Resistance R7 is connected to the base of TRQ7, the cathode of SBD (Schottky barrier diode) D2 to the collector, and the base of output TRQ3 to the emitter; and the other terminal of resistance R7 is connected to the base of phase dividing stage TRQ2, and the anode of SBD.D2 to the base of off-buffer poststage TRQ6. When either of input terminals 1 is at ''0'', TRQ1 turns on and then TRs Q2, Q3, Q4, and Q7 turn off, so that ''1'' will appear at output terminal 3. When a high voltage is applied to terminal 3 in this state, TRs Q5 and Q6 also turn off and no current flows into the output until the output voltage becomes high enough to break down two emitter junction parts of TRs Q5 and Q6. Thus, even when voltage Vcc of electric power source terminal 2 is 5V, output dielectric strength VOB is not less than 17V and when VCC is OV, VOB is 12V, improving the output dielectric strength greatly.

17. 发明专利

JPS55163918A LOGIC GATE CIRCUIT 失效
公开(公告)号：JPS55163918A
公开(公告)日：1980-12-20
申请号：JP7141179
申请日：1979-06-07
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K19/088
摘要： PURPOSE:To increase output dielectric strength by combining pulldown transistors with phase-dividing stage and output-side transistors. CONSTITUTION:When either input terminal 1 is held at a level of ''0'', input-side and power-side transistors Q1 and Q7 conduct and phase-dividing stage and output- stage transistors Q2 and Q3 become unconductive, so that an output terminal where output-side and pulldown transistors Q3 and Q4 are also cut off will be held at a level of ''1''. In this state, when a high voltage is applied to terminal 3 from the outside, prior-stage and post-stage transistors Q5 and Q6 of an off-buffer become unconductive and no current flows to the output until an enough voltage to break down the emitter junction between both the transistors. Therefore, when an electric power voltage is 5V in this case, the output voltage is 17V or more and when 0V, it is 12V, so that the output dielectric strength will increase remarkably as compared with the conventional dielectric strength of 6V, etc.

18. 发明专利

JPS53123637A GATE CIRCUIT 失效
公开(公告)号：JPS53123637A
公开(公告)日：1978-10-28
申请号：JP3887377
申请日：1977-04-04
申请人： NIPPON ELECTRIC CO
发明人： MORI SUSUMU
IPC分类号： H03K19/084 , H01Q1/24 , H03K19/088 , H03K19/20
摘要： PURPOSE:To realize a simple-constitution gate circuit which as two threshold voltages and outputs three signals different in the level with respect to input signals.

你已经成功收藏专利！

检索式保存成功!

IPRDB