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    • 11. 发明专利
    • Digital communication system
    • 数字通信系统
    • JPS5927632A
    • 1984-02-14
    • JP13771582
    • 1982-08-06
    • Mitsubishi Electric Corp
    • MURAKAMI MASAHIKO
    • G10L11/00G10L13/00G10L19/00G10L25/00H04B1/66H04B1/7143H04B14/04H04J13/00
    • H04B1/66
    • PURPOSE:To attain the frame synchronism of a transmitted characteristic parameter value without any frame synchronizing circuit, by transmitting a hopping period and a transmission period of the characteristic parameter while keeping the relation of an integer multiple. CONSTITUTION:Frames F1, F2, F3 accommodate characteristic parameters a1, b1, c1, n1, a2, b2, c2, n2, a3, b3, c3, n3 in a frame train of the characteristic parame ters. The code train of a code M controlling the frequency hopping synchronizing with each frame of the characteristic parameters is transmitted by using the frequency hopping system for the secondary modulating system. The transmission is performed in this case so that the hopping period and the transmission period of the characteristic parameters are made coincident.
    • 目的:通过传输特征参数的跳变周期和传输周期,同时保持整数倍的关系,获得没有任何帧同步电路的传输特性参数值的帧同步。 构成:帧F1,F2,F3适应特征参数的帧序列中的特征参数a1,b1,c1,n1,a2,b2,c2,n2,a3,b3,c3,n3。 通过使用用于二次调制系统的跳频系统来发送控制与特征参数的每个帧同步的跳频的码M的码串。 在这种情况下执行传输,使得特征参数的跳变周期和传输周期一致。
    • 14. 发明专利
    • RECEIVER
    • JPS63138824A
    • 1988-06-10
    • JP28484286
    • 1986-11-29
    • MITSUBISHI ELECTRIC CORP
    • MURAKAMI MASAHIKO
    • H04K3/00H04B1/715H04J13/00
    • PURPOSE:To simplify the titled receiver and to make the size small by providing a filter bank to a high frequency amplifier stage so as to utilize it for the detection of an interference wave in a frequency hopping system receiver. CONSTITUTION:A signal from an antenna 10 is inputted to a filter bank 13 comprising high frequency band pass filters 1a - 1n and high frequency amplifiers 2a - 2n. A level detector 3 detects each output level of the amplifiers 2a - 2n and stores it. A switch 4 supplies a desired high frequency signal to a mixer 5 by using a switching signal of a hopping pattern generator 9. Since the output frequency of a local oscillator 8 is switched by the pattern generator 9, the reception signal is amplified by an intermediate wave amplifier 6 and demodulated by a demodulator 7. A signal other than the desired channel given by the pattern generator 9 is fed via the switch 4 to the discriminator 11, where the presence of an interference wave is discriminated.
    • 17. 发明专利
    • Digital communication device
    • 数字通信设备
    • JPS59110241A
    • 1984-06-26
    • JP22225182
    • 1982-12-15
    • Mitsubishi Electric Corp
    • MURAKAMI MASAHIKO
    • H04L7/00H04B1/7136H04B1/7156H04J13/00H04L7/04
    • H04L7/043
    • PURPOSE:To omit a frequency dividing circuit for generating a data clock by generating the data clock in correspondence with the period of a low-speed pseudo-random code. CONSTITUTION:A transmitter and a receiver are each equipped with a generator 5a for the low-speed pseudo-random code for synchronism acquisition, generator 5b for a high-speed pseudo-random code whose start position is controlled periodically by the low-speed pseudo-random code, and a pseudo-random code generator 5 having a switching circuit 5d which switches and outputs outputs of the generators 5a and 5b according to a control signal. Then, the communication controlled by the low-speed pseudo-random code held in a synchronous state previously is carried out during the transmission of a signal for synchronism acquisition and in a reception waiting state, and the communication controlled by the high-speed pseudo-random code is carried out after synchronism is established. Then a period extracting circuit 5c which extracts the period of the output of the generator 5a is provided and the output of the circuit 5c is used as the data clock for data transmission.
    • 目的:省略分频电路,用于通过产生与低速伪随机码周期对应的数据时钟来产生数据时钟。 构成:发射机和接收机各配备有用于同步获取的低速伪随机码的发生器5a,用于高速伪随机码的发生器5b,其高速伪随机码的起始位置由低速伪随机码周期性地控制 以及伪随机码发生器5,其具有根据控制信号切换并输出发生器5a和5b的输出的切换电路5d。 然后,在用于同步捕获的信号的发送和接收等待状态下,先前保持在同步状态的低速伪随机码所控制的通信被执行,并且由高速伪随机码控制的通信, 随机码在同步建立后进行。 然后提供提取发生器5a的输出周期的周期提取电路5c,并且使用电路5c的输出作为用于数据传输的数据时钟。
    • 18. 发明专利
    • DIGITAL TRANSMITTER-RECEIVER
    • JPH04280136A
    • 1992-10-06
    • JP6525891
    • 1991-03-07
    • MITSUBISHI ELECTRIC CORP
    • MURAKAMI MASAHIKO
    • H04J13/00H04B1/713H04L7/00H04L12/28H04W24/00H04W56/00H04W72/04H04W74/04H04W74/06H04W84/12
    • PURPOSE:To realize the digital transmitter-receiver with a short polling interval in the polling system transmitter-receiver employing the frequency hopping system. CONSTITUTION:A signal from a main station is mixed with a local signal at a reception circuit 20 via an antenna 18 and a high frequency changeover device 19 and a demodulation circuit 20 demodulates a data. A hopping pattern signal from the main station is subject to synchronization acquisition by a synchronization acquisition circuit 24, and a synchronization hold circuit 25 applies synchronization holding to the signal based thereon to control a hopping pattern generating circuit 23 to control a local signal generating circuit 22. A synchronization holding discrimination circuit 26 checks the synchronization holding state after a prescribed time to control a hopping pattern generating circuit 23 so as to omit the succeeding synchronization holding when the synchronization holding is consecutive. When the synchronization holding state is valid up to a succeeding synchronization holding time, the succeeding synchronization acquisition is omitted and polling is implemented immediately, then the polling interval is reduced.