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11. 发明专利

JP2006269774A Substrate for semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件基板及其制造方法
公开(公告)号：JP2006269774A
公开(公告)日：2006-10-05
申请号：JP2005086106
申请日：2005-03-24
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： OTANI KATSUMI , YOSHIDA TAKAYUKI , YAGO MASATOSHI , SUZUKI HIROAKI , FURUYA KEISUKE
IPC分类号： H01L23/12
摘要： PROBLEM TO BE SOLVED: To adjust the electric characteristics of wiring without increasing the outer shape size of a semiconductor device.
SOLUTION: For this substrate for the semiconductor device, linear wiring 6 is formed on one and the other surfaces of an insulation base material 1, and a semiconductor chip is loaded on the insulation base material 1. On the inner peripheral surface of a through-hole 2 passing through the insulation base material 1, helical wiring 3 electrically connecting the linear wiring 6 on one and the other surfaces is provided. Thus, an inductance without the need of a large wiring region is provided, and the substrate for the semiconductor device capable of controlling the electric characteristics of the semiconductor device for high frequency signals by the inductance without increasing the outer shape size is provided.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：在不增加半导体器件的外形尺寸的情况下调整布线的电特性。解决方案：对于这种用于半导体器件的衬底，线性布线6形成在绝缘基底材料1的一个表面和另一个表面上，半导体芯片被装载在绝缘基底材料1上。在内周面设置穿过绝缘基材1的通孔2，在一个面和另一个表面上电连接线性布线6的螺旋布线3。因此，提供了不需要大布线区域的电感，并且提供了能够通过电感来控制用于高频信号的半导体器件的电特性而不增加外形尺寸的半导体器件用基板。版权所有（C）2007，JPO＆INPIT

12. 发明专利

JP2006261142A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006261142A
公开(公告)日：2006-09-28
申请号：JP2005072119
申请日：2005-03-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FURUYA KEISUKE , YOSHIDA TAKAYUKI , SUZUKI HIROAKI , OTANI KATSUMI
IPC分类号： H01L23/12
CPC分类号： H01L2224/16225 , H01L2224/48095 , H01L2224/49171 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a small and highly reliable semiconductor device mounted with a semiconductor element with a number of pins. SOLUTION: In the semiconductor device, at least single set of semiconductor elements 2, 3 is mounted on one surface of a wiring board and external connection terminals such as solder balls 7 are formed on the other surface. In this device, the wiring board 1 is provided with a first wiring region 9 having a wiring patterns 5 connected to the semiconductor elements 2, 3 and the solder balls 7; a second wiring region 11 having pads 12 for electric characteristic test which is provided on the external periphery of the first wiring region 9 with a slit 10 sandwiched, and is electrically connected to the semiconductor elements 2, 3 on the same surface as the mounting surface of the semiconductor elements 2, 3. With this configuration, an electronic characteristic test can be executed for all terminals of the semiconductor elements 2, 3 via the solder balls 7 and the test pads 12. After the test, the second wiring region 11 may be removed. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供安装有具有多个引脚的半导体元件的小而高可靠性的半导体器件。解决方案：在半导体器件中，至少一组半导体元件2,3安装在布线板的一个表面上，而在另一个表面上形成诸如焊球7的外部连接端子。在该装置中，布线基板1具备：第一布线区域9，其具有与半导体元件2,3和焊球7连接的布线图案5; 第二布线区域11具有用于电特性测试的焊盘12，该第二布线区域11设置在第一布线区域9的外周上，其间夹有狭缝10，并且在与安装表面相同的表面上与半导体元件2,3电连接通过这种结构，可以通过焊球7和测试焊盘12对半导体元件2,3的所有端子执行电子特性测试。在测试之后，第二布线区域11可以被删除版权所有（C）2006，JPO＆NCIPI

13. 发明专利

JP2005317737A Semiconductor device and manufacturing method thereof 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005317737A
公开(公告)日：2005-11-10
申请号：JP2004133403
申请日：2004-04-28
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUMOTO KATSUYOSHI , YOSHIDA TAKAYUKI , MATSUMURA KAZUHIKO , KAINO NORIYUKI , KAWABATA TAKESHI
IPC分类号： H01L23/12 , H01L21/56 , H01L21/60
CPC分类号： H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To prevent an electrode which is not electrically connected from being left when a semiconductor device is mounted on a flat motherboard as the curvature quantity of the semiconductor device increases. SOLUTION: The semiconductor device has an external terminal 5 for connection with an external circuit on one surface and the opposite-side surface of a semiconductor substrate 2 where a semiconductor element 1 is mounted. The semiconductor element 1 and one surface of the semiconductor substrate 2 are opposed to each other and electrically connected together through metal projections 7, underfill resin 4 is arranged between the semiconductor element 1 and semiconductor substrate 2, and resin layers 6 are provided on the opposite surface of the semiconductor substrate 2. Consequently, when thermal stress operates owing to temperature variation, curvature caused by the underfill resin 4 is generated in the opposite directions to the curvature caused by the resin layers 6 on the surface of the semiconductor substrate 2 where the external electrode 5 is present, thereby reducing the curvature quantity of the semiconductor device. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了防止半导体器件安装在平板母板上时没有电连接的电极留在半导体器件的曲率上增加。解决方案：半导体器件具有外部端子5，用于与安装半导体元件1的半导体衬底2的一个表面上的外部电路和相对侧表面连接。半导体元件1和半导体基板2的一个表面彼此相对并且通过金属突起7电连接在一起，底部填充树脂4被布置在半导体元件1和半导体基板2之间，树脂层6设置在相对的因此，当由于温度变化而发生热应力时，由底部填充树脂4引起的曲率在与半导体衬底2的表面上的树脂层6所引起的曲率相反的方向上产生，其中存在外部电极5，从而减小半导体器件的曲率。版权所有（C）2006，JPO＆NCIPI

14. 发明专利

JP2008135688A Semiconductor device, and method of manufacturing semiconductor device 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：JP2008135688A
公开(公告)日：2008-06-12
申请号：JP2007147572
申请日：2007-06-04
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KATO YUTAKA , SUZUKI HIROAKI , UEDA NAOTO , AOKURA ISAMU , YOSHIDA TAKAYUKI , HONDO TAKUMA
IPC分类号： H01L23/34 , H01L21/56
CPC分类号： H01L23/3128 , H01L21/56 , H01L23/3677 , H01L23/4334 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/97 , H01L2224/32225 , H01L2224/32245 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/15311 , H01L2924/16151 , H01L2924/16152 , H01L2924/16251 , H01L2924/181 , H01L2924/00012 , H01L2224/83 , H01L2224/85 , H01L2924/00 , H01L2224/05599
摘要： PROBLEM TO BE SOLVED: To prevent a thin metal wire from being short-circuited by resin fluid generated when sealing a semiconductor device whose part of a heat conductor is exposed from a sealing resin to the outside, so that the quality is improved. SOLUTION: The semiconductor device includes a semiconductor element 1, a heat conductor 91 facing a main surface of the semiconductor element 1, and a sealing resin 6 for sealing at least part of the semiconductor element 1 and part of the heat conductor 91. In the semiconductor device, the surface of the heat conductor 91 being opposite to the other surface facing the main surface of the semiconductor element 1 is partially exposed from the sealing resin 6 to the outside. Further, an aperture 11 penetrating in a substrate thickness direction is disposed on part of the surface on which the exposed portion of the heat conductor 91 is formed. This enables resin injection from the opening 11 facing the main surface of the semiconductor element 1, so that the quality is maintained. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为了防止当将热导体的一部分从密封树脂暴露于外部的半导体器件密封时产生的树脂流体短路金属线，从而提高质量。解决方案：半导体器件包括半导体元件1，面向半导体元件1的主表面的热导体91和用于密封半导体元件1的至少一部分和热导体91的一部分的密封树脂6 在半导体装置中，与半导体元件1的主面相对的另一面相对的导热体91的表面部分地从密封树脂6露出到外部。此外，在形成有热导体91的露出部分的部分表面上设置有沿基板厚度方向贯通的孔11。这使得能够从开口11朝向半导体元件1的主表面注入树脂，从而保持质量。版权所有（C）2008，JPO＆INPIT

15. 发明专利

JP2008004570A Process and apparatus for manufacturing resin sealed semiconductor device, and resin sealed semiconductor device 审中-公开
标题翻译：用于制造树脂密封半导体器件和树脂密封半导体器件的工艺和装置
公开(公告)号：JP2008004570A
公开(公告)日：2008-01-10
申请号：JP2006169477
申请日：2006-06-20
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： ITO TETSUO , YOSHIDA TAKAYUKI , FUKUDA TOSHIYUKI , OCHI TAKAO
IPC分类号： H01L21/56
CPC分类号： B29C45/0025 , B29C45/14655 , B29C45/2708 , B29C45/34 , B29C2045/0027 , H01L21/561 , H01L21/565 , H01L23/3121 , H01L23/3128 , H01L24/48 , H01L24/97 , H01L25/105 , H01L2224/48091 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/15787 , H01L2924/181 , H01L2924/1815 , H01L2224/85 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide an apparatus and a method for manufacturing a resin sealed semiconductor device having an external electrode provided on the surface of a substrate for mounting a semiconductor element under a state ensuring good yield while enhancing productivity. SOLUTION: In the apparatus for manufacturing a resin sealed semiconductor device, a resin sealing die 20 having a cavity 21 is provided with an opening 29a for injecting sealing resin 25 toward the cavity 21, and an opening 30a for releasing air from the cavity 21 when resin is injected. Not only the resin injection opening 29a but also the air release opening 30a opens to the top surface portion 21a of the cavity 21. Consequently, resin burr can be prevented from adhering to an external terminal 4A provided on the surface portion 2a of a substrate 2 even when the resin burr is left in the resin injection opening 29a or the air release opening 30a. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种用于制造树脂密封半导体器件的装置和方法，该树脂密封半导体器件具有设置在基板的表面上的用于在确保良好产量的状态下安装半导体元件的外部电极，同时提高生产率。解决方案：在树脂密封半导体器件的制造装置中，具有空腔21的树脂密封模具20设置有用于将密封树脂25朝向空腔21注入的开口29a，以及用于从空腔21释放空气的开口30a 树脂注入时的空腔21。不仅树脂注入开口29a而且空气释放开口30a向空腔21的上表面部分21a开口。因此，可以防止树脂毛刺粘附到设置在基板2的表面部分2a上的外部端子4A 即使当树脂毛刺留在树脂注入口29a或排气口30a中时。版权所有（C）2008，JPO＆INPIT

16. 发明专利

JP2006165275A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006165275A
公开(公告)日：2006-06-22
申请号：JP2004354760
申请日：2004-12-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： FUKUTO KENJI , YOSHIDA TAKAYUKI , SUZUKI HIROAKI , OKI SHIGERU
IPC分类号： H01L23/12 , H01L25/10 , H01L25/11 , H01L25/18
CPC分类号： H01L24/96 , H01L24/73 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48227 , H01L2224/73204 , H01L2224/73253 , H01L2224/73265 , H01L2225/06558 , H01L2924/15156 , H01L2924/15311 , H01L2924/3511 , H01L2924/00012 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To suppress the warp of a semiconductor chip enough to suppress the electric characteristic change of the semiconductor chip and the breaking of wires in wiring vias while intending to thin and lighten the semiconductor device. SOLUTION: The semiconductor device employs a structure having a semiconductor chip 2 mounted on a dish-like wiring board 1 having warped parts 1a at the periphery. This suppresses the shape change such as warp, etc. of the chip 2, and accompanying stresses due to the heat history on manufacturing and an external force at inspection or in the use, and suppresses the electric characteristic change of the semiconductor chip 2 and the breaking of wires in wiring vias. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了抑制半导体芯片的翘曲，足以抑制半导体芯片的电特性变化和布线通孔中的导线的断裂，同时要减薄和减轻半导体器件。解决方案：半导体器件采用具有半导体芯片2的结构，该半导体芯片2安装在具有周边的翘曲部分1a的盘状布线板1上。这抑制了芯片2的翘曲等的形状变化，以及由于制造时的热历史和检查或使用时的外力引起的伴随的应力，并且抑制了半导体芯片2的电特性变化接线通孔中的电线断线。版权所有（C）2006，JPO＆NCIPI

17. 发明专利

JP2006024656A Semiconductor device and its manufacturing method 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2006024656A
公开(公告)日：2006-01-26
申请号：JP2004199948
申请日：2004-07-07
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUMURA KAZUHIKO , YOSHIDA TAKAYUKI
IPC分类号： H01L21/60
CPC分类号： H01L24/73 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73204 , H01L2224/83102 , H01L2224/92125 , H01L2924/01019 , H01L2924/01029 , H01L2924/01079 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device which will not have cracks or liftings, even if such a brittle material as a Low-k one is used for the insulation film of a semiconductor chip, and to provide its manufacturing method. SOLUTION: In the semiconductor device, the semiconductor chip 1 is mounted on a mount body, such as a substrate 5 formed with electrode patterns 6, and is fixed to the internal bottom face of a recessed support frame 10 by the back surface opposite from the electrode surface thereof. The end of the support frame 10 is fixed to the electrode surface of the substrate 5. Accordingly, solder bumps 4 formed on Al electrodes 2 of the semiconductor chip 1 and the corresponding electrode patterns 6 are arranged to face each other at a prescribed space apart from each other. The solder bumps 4 and electrode patterns 6, arranged facing each other, are electrically connected by an easily deformable conductive resin 11 arranged in the space in between. Since the solder bumps 4 and the electrode patterns 6 are electrically connected by the conductive resin 11, under a state such that the semiconductor chip 1 hangs in midair, stress generated in the connecting portions between the solder bumps 4 and the electrode patterns 6 due to thermal expansion and shrinkage of the substrate 5, etc. can be relaxed the deformation of the conductive resin 11, resulting in prevention of the concentration of stress in the periphery of the bumps and thereby preventing destruction due to stress of an insulation film 1a of the semiconductor chip 1. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：为了提供一种不会产生裂纹或提升的半导体器件，即使使用诸如Low-k的这种脆性材料用于半导体芯片的绝缘膜，并且提供其制造方法。解决方案：在半导体器件中，半导体芯片1安装在诸如形成有电极图案6的基板5的安装体上，并且通过背面固定到凹形支撑框架10的内底面与其电极表面相对。支撑框架10的端部被固定到基板5的电极表面。因此，形成在半导体芯片1的Al电极2上的焊料凸点4和相应的电极图案6被布置为以规定的间隔彼此面对从彼此。彼此相对配置的焊料凸块4和电极图案6通过布置在其间的空间中的容易变形的导电树脂11电连接。由于焊锡凸块4和电极图案6通过导电树脂11电连接，所以在半导体芯片1悬空的状态下，由于焊料凸点4和电极图案6之间的连接部分产生的应力由于可以缓和基板5等的热膨胀和收缩导致导电树脂11的变形，从而防止凸块周围的应力集中，从而防止由于绝缘膜1a的应力引起的破坏半导体芯片1.版权所有（C）2006年，JPO＆NCIPI

18. 发明专利

JP2005260134A Semiconductor device and electrode manufacturing method therefor 有权
标题翻译：半导体器件及其电极制造方法
公开(公告)号：JP2005260134A
公开(公告)日：2005-09-22
申请号：JP2004072535
申请日：2004-03-15
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUMURA KAZUHIKO , YOSHIDA TAKAYUKI , OCHI YUTAKA , MIYAZAKI HIROYUKI
IPC分类号： H01L21/60
CPC分类号： H01L2224/11 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To prevent a failure in the normal operation of a chip in which the failure occurs when contact resistance increases between a UBM (Under Barrier Metal) or a rewiring metal on the electrode of the semiconductor chip and an oxide film on the surface of an electrode.
SOLUTION: A semiconductor device has a bump formed on the electrode of the semiconductor chip via the UBM, or on a metal wire that is formed on the electrode forming surface of the semiconductor chip and electrically connected to the electrode of the semiconductor chip. The semiconductor device also has a select circuit 21 which is on a line connecting the electrode of the signal terminal 20 of the semiconductor chip to a buffer circuit for a signal terminal, and connected to the GND or a power supply. A voltage higher than the breakdown voltage of the metal oxide film is applied to the metal oxide film of an electrode material which is formed in the interface between the electrode of the semiconductor chip and the UBM or the rewiring metal, to break the metal oxide film.
COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题为了防止在半导体芯片的电极上的UBM（障碍金属）或重新布线金属之间的接触电阻增加时发生故障的芯片的正常工作失败，以及氧化物电极表面上的膜。解决方案：半导体器件具有通过UBM形成在半导体芯片的电极上的凸块，或者形成在半导体芯片的电极形成表面上并电连接到半导体芯片的电极的金属线上。半导体器件还具有选择电路21，该电路21将半导体芯片的信号端子20的电极与信号端子的缓冲电路连接，并连接到GND或电源。将高于金属氧化物膜的击穿电压的电压施加到形成在半导体芯片的电极与UBM或重新布线金属之间的界面中的电极材料的金属氧化物膜上，以破坏金属氧化物膜。版权所有（C）2005，JPO＆NCIPI

19. 发明专利

JP2005123379A Resin sealed semiconductor device 有权
标题翻译：树脂密封半导体器件
公开(公告)号：JP2005123379A
公开(公告)日：2005-05-12
申请号：JP2003356223
申请日：2003-10-16
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： MATSUMOTO KATSUYOSHI , YOSHIDA TAKAYUKI , MATSUMURA KAZUHIKO , KAINO NORIYUKI , KAWABATA TAKESHI
IPC分类号： H01L21/60
CPC分类号： H01L2224/05554 , H01L2224/48091 , H01L2224/48247 , H01L2224/49 , H01L2224/4903 , H01L2224/49051 , H01L2224/49171 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide such a structure that can prevent a leakage among wires through a carbon containing in a sealing resin, and provide a structure of an electromagnetic shield that can prevent discharging and entry of electromagnetic waves from a semiconductor device or a wire and to the outside. SOLUTION: A dummy wire 10 is provided outside so as to cover a wire 3 entirely at a narrower pitch and much more than the wire 3. Due to such a structure, even if carbon particles exist, the carbon particles larger in size than an interval between the dummy wires 10 is impossible to enter the inside, generating no leakage between the wires 3. In addition, the carbon particles smaller in size than an interval between the dummy wires 10 are possible to enter the inside, however, they are smaller than an interval between the wires 3, resulting in no leakage between the wires 3. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供这样的结构，其可以防止电线通过密封树脂中含有的碳之间的泄漏，并且提供可以防止电磁波从半导体器件放电和进入的电磁屏蔽的结构或电线和外部。解决方案：虚线10被设置在外侧，以完全以更窄的间距覆盖线3，并且比线3多得多。由于这样的结构，即使存在碳颗粒，碳粒子尺寸更大虚拟线10之间的间隔不能进入内部，不会在导线3之间产生泄漏。此外，尺寸小于虚拟线10之间的间隔的碳粒子可能进入内部，然而，它们小于电线3之间的间隔，导致电线3之间没有泄漏。版权所有（C）2005，JPO＆NCIPI

20. 发明专利

JP2005033061A Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2005033061A
公开(公告)日：2005-02-03
申请号：JP2003271964
申请日：2003-07-08
申请人： Matsushita Electric Ind Co Ltd , 松下電器産業株式会社
发明人： KAINO NORIYUKI , YOSHIDA TAKAYUKI , MATSUMURA KAZUHIKO , MATSUMOTO KATSUYOSHI , KAWABATA TAKESHI
IPC分类号： H01L23/12 , H01L21/60
CPC分类号： H01L2224/11
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device for realizing the pitch narrowing of wiring corresponding to high density mounting by an inexpensive means and to provide a method for manufacturing it. SOLUTION: A partial insulating resin layer 4 is provided with an insulating resin layer 4a in an upper layer formed so as to be extended from an insulating resin layer 4b in a lower layer. In an anisotropic deposition process, a portion 10 where metal is not deposited under the shadow of metallic irradiation is formed on resin just under the extended part of the upper layer resin so that an insulating distance can be arranged with a vertical wiring interval. Thus, it is possible to provide a semiconductor device constituted of narrow pitch and highly dense metallic wiring 7a without making it necessary to arrange any horizontal insulating distance between wiring. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供一种半导体器件，用于通过廉价的方法实现对应于高密度安装的布线的间距变窄，并提供其制造方法。解决方案：部分绝缘树脂层4在上层中设置有绝缘树脂层4a，其形成为从下层中的绝缘树脂层4b延伸。在各向异性沉积工艺中，在刚好在上层树脂的延伸部分的树脂上的树脂上形成在金属照射阴影下不沉积金属的部分10，使得可以以垂直布线间隔布置绝缘距离。因此，可以提供由窄间距和高致密金属布线7a构成的半导体器件，而不需要在布线之间布置任何水平绝缘距离。版权所有（C）2005，JPO＆NCIPI

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