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11. 发明专利

JPS6149271A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6149271A
公开(公告)日：1986-03-11
申请号：JP17112184
申请日：1984-08-16
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , ASANO HAJIME , SHIMIZU MASAHISA , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/8007
摘要： PURPOSE:To make an element highly functional by connecting respective receiving and transmitting control means and an execution processing unit through a data shunt or data confluent means to a ring-shaped asynchronous bus and forming these in a semiconductor element. CONSTITUTION:An input interface part 11 as a receiving control means is connected through a confluent mechanism 15 to an asynchronous self-travelling ring bus 131. Plural execution processing units 141 and 145 are connected through a bus adaptor 17 to the asynchronous self-travelling ring bus 131. An output interface 12 as a transmitting control means is connected through a shunt mechanism 16 to other asynchronous self-travelling ring bus 132. The above-mentioned execution processing units 143 and 145 and 146 and 147 are connected through the bus adaptor 17 to the asynchronous self-travelling ring bus 132.
摘要翻译：目的：通过将各个接收和发送控制装置和执行处理单元通过数据分流或数据汇合装置连接到环形异步总线并将其形成在半导体元件中，使元件具有高度的功能。构成：作为接收控制装置的输入接口部分11通过汇合机构15连接到异步自行车环形总线131.多个执行处理单元141和145通过总线适配器17连接到异步自行车环作为发送控制装置的输出接口12通过分流机构16连接到其他异步自行车环形总线132.上述执行处理单元143和145和146和147通过总线适配器17连接到异步自行车环形总线132。

12. 发明专利

JPS5971553A Simulation device for digital circuit 失效
标题翻译：数字电路仿真器件
公开(公告)号：JPS5971553A
公开(公告)日：1984-04-23
申请号：JP18200082
申请日：1982-10-15
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , OKAMOTO TOSHIYA , TOKURA TAKESHI , SHIMIZU MASAHISA , KAMIMURA KAZUO
IPC分类号： G06F11/25 , G06F11/26 , G06F17/50 , G06F19/00
CPC分类号： G06F11/261
摘要： PURPOSE:To attain parallel simulation of logical element of parallel operation, by storing a data at each element of a digital circuit and storing the preceding data, and operating the element to which an input data is set. CONSTITUTION:When the input data is given to an input/output sub-system 1, packets 11-13 corresponding to the input are formed and given to an execution control unit 2 via an arbiter 14. The unit 2 sets the data to templates 22, 23 via a distributor DIS21. The templates store the data relating to each element included in a digital circuit to be simulated, and when the required data is finished to be set to the templates, they are activated and transmit the data to an ALU 26 via the arbiter 25. The ALU26 performs required operation and sets the result to the templates via the DIS21. A function memory 3 stores the data before the noted generation, and the data read from the memory 3 is set to the template 24 allowing to perform simulation in parallel according to the career data.
摘要翻译：目的：通过在数字电路的每个元素处存储数据并存储前一个数据，并且操作设置了输入数据的元素，来实现并行操作的逻辑元件的并行仿真。构成：当输入/输出子系统1输入数据时，形成与输入对应的数据包11-13，并通过仲裁器14给予执行控制单元2.单元2将数据设置为模板22 ，23通过分配器DIS21。模板存储与要被仿真的数字电路中包含的每个元素有关的数据，并且当所需数据完成设置为模板时，它们被激活，并且经由仲裁器25将数据发送到ALU 26. ALU26 执行所需的操作，并通过DIS21将结果设置为模板。功能存储器3存储所述生成之前的数据，并且将从存储器3读取的数据设置为模板24，允许根据职业数据并行进行模拟。

13. 发明专利

JPS5969861A Simulating device of digital circuit 失效
标题翻译：模拟数字电路设备
公开(公告)号：JPS5969861A
公开(公告)日：1984-04-20
申请号：JP18093182
申请日：1982-10-14
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , OKAMOTO TOSHIYA , TOKURA TAKESHI , SHIMIZU MASAHISA , KAMIMURA KAZUO
IPC分类号： G06F11/25 , G01R31/28 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5045
摘要： PURPOSE:To detect the error of circuit design easily by inputting directly the data of a circuit diagram, processing the circuit diagram data by data driving type graphic language and displaying the process of simulation together with the circuit diagram. CONSTITUTION:A circuit diagram input part 41 inputs a circuit diagram to be simulated by a display and a light pen in a conversational format. In a partial circuit to be frequently used out of a circuit, the detailed circuit diagram data are previously stored in a partial circuit storing part 42 and are to be used at the time of input. Data from the input part 41 and the storage part 42 are coupled each other by a partial circuit coupling part 43 to form a main coupled diagram data. A loop structure converting part 44 searches the loop structure included in the circuit diagram data, cuts off the loop and converts the cut loops into a return structure part. A dividing part 45 is divided into an operation part and a state storing part. These data are processed by a data driving type processing part 46.
摘要翻译：目的：通过直接输入电路图的数据，通过数据驱动类型图形语言处理电路图数据，并与电路图一起显示仿真过程，轻松检测电路设计的误差。构成：电路图输入部分41输入由会话形式的显示器和光笔模拟的电路图。在经常从电路中使用的部分电路中，详细的电路图数据预先存储在部分电路存储部分42中，并且在输入时使用。来自输入部分41和存储部分42的数据通过部分电路耦合部分43彼此耦合以形成主耦合图数据。环路结构转换部分44搜索包括在电路图数据中的环路结构，切断环路并将切割的环路转换成返回结构部分。分割部分45分为操作部分和状态存储部分。这些数据由数据驱动型处理部分46处理。

14. 发明专利

JPH0475174A SYSTEM DEVELOPMENT DEVICE 失效
公开(公告)号：JPH0475174A
公开(公告)日：1992-03-10
申请号：JP19182190
申请日：1990-07-17
申请人： MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP , SHARP KK
发明人： TERADA HIRONORI , NISHIKAWA HIROAKI , HINE TOSHIHARU , NISHIKAWA YOICHIRO , HARA HIDEJI , INAOKA MIE , YAMAZAKI TETSUO , SHIMA KENJI , YOSHIDA SHINICHI
IPC分类号： G06F9/06 , G06F17/50
摘要： PURPOSE:To describe the relation between modules through easy operation while keeping adjustability by receiving 1st data information from a retrieval means, and substituting the data structure information of 2nd data information with the data structure information of the 1st data and updating the data. CONSTITUTION:A user specifies areas corresponding to the 1st and 2nd pieces of data information by utilizing position specifying means 1 and 2 and supplies the coordinates of the area where the 1st data information is to be displayed to a calculating means 5 and the coordinates of the area where the 2nd data information is displayed to an update means 6. The retrieval means 5 retrieves a storage means 3 according to the given coordinates to extract the 1st data information and the update means 6 extracts the 2nd data information, updates the 2nd data information with the 1st data information, and stores the result in the storage means 3 again. The 2nd data information which is stored is displayed in the corresponding area on a display screen 8 by display means 7 and 8. Thus, the data information which is already generated in a 1st module is reused to generate or update the 2nd module information. Consequently, the operation is reducible.

15. 发明专利

JPS6421530A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS6421530A
公开(公告)日：1989-01-24
申请号：JP17783687
申请日：1987-07-15
申请人： MITSUBISHI ELECTRIC CORP
发明人： TAMURA TOSHIYUKI , KOMORI NOBUFUMI , TAKADA HIDEHIRO , YAMAZAKI TETSUO , TERADA HIRONORI , ASADA KATSUHIKO
IPC分类号： G06F5/08 , G06F13/38 , H04L1/24
摘要： PURPOSE:To transfer data within a short transfer time in case of transferring the small quantity of data and to obtain a sufficient buffering function in case of transferring the many quantity of data by connecting a by-pass route between the going route of a data transfer route and its return route. CONSTITUTION:When a flip flop 30 in a constitutional unit 120 for repeated states is in a set state, data are inputted from an input part 110, and when the data are transferred to a data latch constituting a shift register, the data are transferred to its corresponding lower data latch 6 through the by-pass route P2. When the flip flop 30 is in a reset state, the inputted data are transferred to the data latch 3 and then transferred to an upper data latch in the succeeding unit and data transferred from the lower data latch in the succeeding unit are transferred to the data latch 6. If data are stagnated in a shift register in the going route, the inputted data are buffered, and in case of no data stagnation, the inputted data can be transferred within a short transfer time.

16. 发明专利

JPS62174856A DATA TRANSMISSION DEVICE 失效
公开(公告)号：JPS62174856A
公开(公告)日：1987-07-31
申请号：JP1754386
申请日：1986-01-28
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F13/20 , G06F13/36 , G06F15/82
摘要： PURPOSE:To accept input data to the limit of the data acceptance by providing a transmission/confluence control gate means corresponding to respective plural parallel transmission lines, opening each transmission/confluence control gate means in a sequentially designated order, and transmitting the data, which have been sent from the corresponding data transmission lines, to the data transmission line on the output side. CONSTITUTION:The device consists of the data transmission means 10 and 20 each having a confluence gate function, which are provided in correspondence to plural parallel transmissions 1 and 2 respectively, and a confluence control means 50 to open the data transmission means each having a confluence gate function in a previously determined order, to transmit the data transmitted from a correspondent transmission line to the transmission line on the output side. Thus, the data sent from the corresponding transmission line are accepted up to the acceptance capacity of the transmission line, and transmitted sequentially to the transmission line on the output side in the least delayed time necessary for the confluence control.

17. 发明专利

JPS6234254A MEMORY ACCESS CONTROLLER 失效
公开(公告)号：JPS6234254A
公开(公告)日：1987-02-14
申请号：JP17392485
申请日：1985-08-06
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F12/06 , G06F13/16
摘要： PURPOSE:To shorten the processing time with a memory access controller by giving accesses after decentralizing them through plural memories even with asynchronizing input data. CONSTITUTION:The packet data consisting two words supplied asynchronously with each other are given successively to a branch control part 3. Each of these packet data containing two words is branched and stored temporarily in registers 41-44 by register controller 51-54. Then the packet data are written to and read out of memories contained in banks 100-400. The data read out of the banks 100-400 are given to a confluence control part 9 for sequential confluence. As a result, the input packet data even when in asynchronizing state can be written and read out of memories after decentralization.

18. 发明专利

JPS6223253A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS6223253A
公开(公告)日：1987-01-31
申请号：JP16360485
申请日：1985-07-23
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F15/16 , G06F5/06 , G06F13/00 , G06F13/36 , G06F15/177 , G06F15/82
摘要： PURPOSE:To rearrange the content of a packet in an optional order by opening each summing gate means in a predetermined order in response to the transmis sion of a transmission enable signal from a data transmission line at the output side and sending the data sent from a corresponding data transmission line to the data transmission line at the output side. CONSTITUTION:Two transmission lines 1, 2 are provided in parallel and summing control gates 10, 20 are provided corresponding to transmission line 1, 2. The joining control section 50 is provided to apply switching control to the summing control gates 10, 20, the joining control section 50 applies switching control to the data transmission lines 10, 20 in a predetermined order to send a data from the data transmission lines 1, 2 to a data transmission line 60 at the output side. Further, it is predetermined that the data transmission line 1 has priority over the data transmission line 2. The summing gates 10, 20 are opened in a predetermined order according to the transmission enable signal sent from the transmission line at the output side and the data sent from the corresponding transmission lines 1, 2 is sent sequentially to the transmission line 60 at the output side.

19. 发明专利

JPS6210729A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS6210729A
公开(公告)日：1987-01-19
申请号：JP15198485
申请日：1985-07-09
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI
IPC分类号： G06F5/06 , G06F13/38
摘要： PURPOSE:To obtain the data transmission equipment which can propagate the data slowly and little by little by providing an indicating means to instruct the transfer timing of the data and a transfer timing control means to control the output timing of at least one C element in accordance with the instruction. CONSTITUTION:When a toggle switch 36 is turned from ON to OFF, the output of an inverter 35a comes to 0, and the data arrive at a C element 7h and stop once. At such a time, a momentary switch 39 is normally OFF, when this is pushed, the clock input of a D type flip flop 31 comes to 1, a Q output comes to 1, the P2 output of a C element 34 comes to 1 and a P1 output comes to 0. Further, since the output of an inverter 35d comes to 0, again, the P2 output of the C element 34 comes to 0 and the P1 output which is an inverting output comes to 1. Since the P1 output of the C element 34 comes to 0 once and comes to 1, a C element 7i returns the P1 output, sends the P2 output to the C element 7j and transmits the data of one word to the next stage. Thus, at the time of the necessity, the data can be slowly propagated.

20. 发明专利

JPS61294949A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS61294949A
公开(公告)日：1986-12-25
申请号：JP13661085
申请日：1985-06-21
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , KOMORI NOBUFUMI , SHIMA KENJI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI
IPC分类号： G06F5/12 , G06F5/06 , G06F9/44 , G06F13/00 , G06F13/36 , G06F15/82
摘要： PURPOSE:To give a large degree of freedom for system architecture by allowing a branch section to discriminate whether or not a data on an input data transmission line is to be branched, and/or to supervise an idle state of a branch data transmission line for branch control and allowing a confluence section to apply confluence control. CONSTITUTION:The branch section gives normally a data of an input data transmission line 10 to an output data transmission line 20 via a branch control section 40, while a branch discrimination section 50 discriminates that the input data is a data to be branched and an idle buffer supervisory section 75 confirms that an idle buffer exists in a branch data transmission line 30, then the input data is branched to the branch data transmission line 30 via the branch control section 40. Further, the confluence section gives normally the data in the input data transmission line 10 to the output data transmission line 20 via a confluence control section 60 and when an idle buffer supervisory section 80 confirms that an idle buffer exists in the input and output data transmission lines 10, 20, the confluence control section 60 confluences the data of a confluence data transmission line 70 to the output data transmission line 20.

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