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1. 发明专利

JPS6149271A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6149271A
公开(公告)日：1986-03-11
申请号：JP17112184
申请日：1984-08-16
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , ASANO HAJIME , SHIMIZU MASAHISA , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8015 , G06F15/8007
摘要： PURPOSE:To make an element highly functional by connecting respective receiving and transmitting control means and an execution processing unit through a data shunt or data confluent means to a ring-shaped asynchronous bus and forming these in a semiconductor element. CONSTITUTION:An input interface part 11 as a receiving control means is connected through a confluent mechanism 15 to an asynchronous self-travelling ring bus 131. Plural execution processing units 141 and 145 are connected through a bus adaptor 17 to the asynchronous self-travelling ring bus 131. An output interface 12 as a transmitting control means is connected through a shunt mechanism 16 to other asynchronous self-travelling ring bus 132. The above-mentioned execution processing units 143 and 145 and 146 and 147 are connected through the bus adaptor 17 to the asynchronous self-travelling ring bus 132.
摘要翻译：目的：通过将各个接收和发送控制装置和执行处理单元通过数据分流或数据汇合装置连接到环形异步总线并将其形成在半导体元件中，使元件具有高度的功能。构成：作为接收控制装置的输入接口部分11通过汇合机构15连接到异步自行车环形总线131.多个执行处理单元141和145通过总线适配器17连接到异步自行车环作为发送控制装置的输出接口12通过分流机构16连接到其他异步自行车环形总线132.上述执行处理单元143和145和146和147通过总线适配器17连接到异步自行车环形总线132。

2. 发明专利

JPS61123968A Data transmitting device 失效
标题翻译：数据传输设备
公开(公告)号：JPS61123968A
公开(公告)日：1986-06-11
申请号：JP24750184
申请日：1984-11-20
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMA KENJI , KOMORI NOBUFUMI , AKECHI MITSUO
IPC分类号： G06F13/36 , G06F13/37 , G06F13/38 , G06F15/16 , G06F15/177 , G06F13/20
CPC分类号： G06F13/38 , G06F15/161
摘要： PURPOSE:To realize an effective and high-speed data transmittance by installing a port sequencer and a daisy chain controller and setting a sequence setting means necessary for the said port sequencer. CONSTITUTION:A bypass is installed consisting of an input port having a input data bus and a input control line, and a output port having a output data bus and a output control line, and a bypass line route is installed consisting of a bypass gate 107, etc. which bypasses a signal of the said input data bus to the said output data bus. Port sequencers 102, 122 and a daisy chain controller 120 are installed to be operated respectively by the signals of the said input control line and the said output control line, and the daisy transfer line as input or output. And, in order to set a transfer function sequence required for the said port sequencer, data processing modules having sequence setting means are cascaded plurally. Thus the daisy chain transmitting of data among plural data processing modules is carried out, resulting in an effective and high-speed data transmittance.
摘要翻译：目的：通过安装端口排序器和菊花链控制器并设置所需端口排序器所需的序列设置手段，实现有效和高速的数据传输。构成：安装有由具有输入数据总线和输入控制线的输入端口组成的旁路，以及具有输出数据总线和输出控制线的输出端口，以及由旁路门107组成的旁路线路由等等，其将所述输入数据总线的信号旁路到所述输出数据总线。端口排序器102,122和菊花链控制器120被安装成分别由所述输入控制线和所述输出控制线的信号和菊花传输线作为输入或输出来操作。并且，为了设定所述端口排序器所需的传递函数序列，具有多个序列设置装置的数据处理模块被级联。因此，执行多个数据处理模块之间的数据的菊花链传输，从而实现有效和高速的数据透射率。

3. 发明专利

JPS6149538A Loop type data transmitter 失效
标题翻译：环型数据传输器
公开(公告)号：JPS6149538A
公开(公告)日：1986-03-11
申请号：JP17120384
申请日：1984-08-16
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , ASANO HAJIME , SHIMIZU MASAHISA , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI
摘要： PURPOSE: To constitute the same function with the loop type data transmitter with less memory capacity and simple interfaces and to facilitate IC-implementation by providing an annular access transmission line.
CONSTITUTION: Input interfaces 150∼152 and output interfaces 153∼155 are connected individually to plural data processors 131∼136. Those interfaces 150∼152 and 153∼155 are connected annularly through active transmission lines 140∼ 145. Those interfaces 150∼152 and 153∼155 and transmission lines 140∼145 are connected through data lines 160∼171, and output ready signals 172∼177, write signals 178∼183, shift signals 184∼189, input ready signals 190∼195, etc., are inputted and outputted between the respective interfaces and transmission lines. Thus, the same function with the loop type data transmitter is constituted with less memory capacity and simple inerfaces, thereby facilitating the IC-implementation.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：与具有较少内存容量和简单接口的循环型数据发射机构成相同的功能，并通过提供环形接入传输线来促进IC实现。构成：输入接口150-152和输出接口153-155分别连接到多个数据处理器131-136。这些接口150-152和153-155通过有源传输线140-145环形连接。这些接口150-152和153-155以及传输线140-145通过数据线160-171连接，并且输出就绪信号172- 如图177所示，写入信号178-183，移位信号184-189，输入就绪信号190-195等在相应的接口和传输线之间被输入和输出。因此，与循环型数据发送器相同的功能由较少的存储容量和简单的内容构成，从而便于IC实现。

4. 发明专利

JPS6149263A Information processing module 失效
标题翻译：信息处理模块
公开(公告)号：JPS6149263A
公开(公告)日：1986-03-11
申请号：JP17210984
申请日：1984-08-16
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMIZU MASAHISA , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , ASANO HAJIME
IPC分类号： G06F15/16 , G06F13/20
摘要： PURPOSE: To remove waste on a hardware without damaging a general characteristic and to further elevate parallel processing by controlling respective parts in accordance with a signal showing a parallel port control part, a direct port control part and an operation part.
CONSTITUTION: A central control part 60, which becomes a control center of a module, consists of an order register 61 fetching a micro-program stored in a main memory device 52, a condition selecting circuit 65 giving a control signal to a sequencer 62, the sequencer 62 controlling a sequence of a micro-order, a micro-program memory 63 and a pipeline register 64. An operation part 40 consists of an operation processing unit 41 and an operation instruction control circuit 42, and fetches the data stored in the main memory device 52 the data from various inport ports and operates. The module has a parallel input port 11, a parallel output port 13 parallel input output ports 21 and 23, a direct input port 31 and a direct output port 32.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：在不破坏一般特性的情况下去除硬件上的废物，并根据显示并行端口控制部分，直接端口控制部分和操作部分的信号控制相应部分，进一步提升并行处理。构成：成为模块的控制中心的中央控制部分60由存储在主存储装置52中的微程序的订单寄存器61，向定序器62提供控制信号的条件选择电路65，控制微顺序的定序器62，微程序存储器63和流水线寄存器64.操作部分40由操作处理单元41和操作指令控制电路42组成，并且获取存储在主存储器件52来自各种入口端口的数据并操作。该模块具有并行输入端口11，并行输出端口13并行输入端口21和23，直接输入端口31和直接输出端口32。

5. 发明专利

JPS6149239A Information processor and emulation device 失效
标题翻译：信息处理器和仿真器件
公开(公告)号：JPS6149239A
公开(公告)日：1986-03-11
申请号：JP17211084
申请日：1984-08-16
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMIZU MASAHISA , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , ASANO HAJIME
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE: To standardize the designing and production and also to cope with various specifications by using information processing modules which have the same structure and can set freely various functions to constitute an information processor.
CONSTITUTION: An information module contains a port 11 exclusive for parallel inputs, a port 13 exclusive for parallel outputs, parallel input/output ports 21 and 23, a port 31 exclusive for series inputs and a port 32 exclusive for series outputs. A data transfer line 16 is set between ports 11 and 13 for direct transfer of the data supplied to the port 11 to the port 13. A control circuit 15 performs the local control of both ports 11 and 13. A central control part 60 consists of an instruction register 61, a microprogram memory 63, etc. and controls the information module. An arithmetic part 40 fetches the data stored in a main memory 52 or the data supplied through various input ports.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：规范设计和生产，并通过使用具有相同结构的信息处理模块来应对各种规格，并可以自由设置各种功能来构成信息处理器。构成：信息模块包含并行输入专用端口11，并行输出专用端口13，并行输入/输出端口21和23，串行输入专用端口31和串行输出专用端口32。在端口11和13之间设置数据传输线路16，用于将提供给端口11的数据直接传送到端口13.控制电路15执行两个端口11和13的本地控制。中央控制部分60由指令寄存器61，微程序存储器63等，并控制信息模块。算术部分40取出存储在主存储器52中的数据或通过各种输入端口提供的数据。

6. 发明专利

JPH0564381B2 失效
公开(公告)号：JPH0564381B2
公开(公告)日：1993-09-14
申请号：JP1754486
申请日：1986-01-28
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F13/20 , G06F13/36 , G06F15/82

7. 发明专利

JPH0475133A PROGRAM DEVELOPING DEVICE 失效
公开(公告)号：JPH0475133A
公开(公告)日：1992-03-10
申请号：JP19181890
申请日：1990-07-17
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , NISHIKAWA HIROAKI , YAMAZAKI TETSUO , INAOKA MIE , SHIMA KENJI , YOSHIDA SHINICHI , HINE TOSHIHARU , NISHIKAWA YOICHIRO , HARA HIDEJI
IPC分类号： G06F9/06
摘要： PURPOSE:To construct a software system with high quality by defining a software system multilaterally by enabling one piece of specification definition information(one function) to be described by using plural expression formats. CONSTITUTION:Graphic editors E1-En each of which is provided with a plotting and editing function according to different expression formats, and a main body device 1 which generates a program according to specification description supplied from a user are provided. The specification definition information to be supplied to object software is inputted by using the plural expression formats and also, in hierarchical manner, and an executable program can be generated from the specification definition information as preserving hierarchical property held by the specification definition information. In such a way, it is possible to express one specification definition by the plural expression formats, and to express one specification definition multilaterally, and to realize prototype environment with superior correspondence with the specification description.

8. 发明专利

JPS6223254A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS6223254A
公开(公告)日：1987-01-31
申请号：JP16360585
申请日：1985-07-23
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F15/16 , G06F5/06 , G06F13/00 , G06F13/36 , G06F15/177 , G06F15/82
摘要： PURPOSE:To send a data through a desired transmission line even when a different kind of data is inputted by discriminating whether or not a transmission enable signal is outputted from plural parallel transmission lines and sending a data to any transmission line according to an identifier attended to the data of the plural transmission lines. CONSTITUTION:An identifier transmission line 2 gives an identifier representing that a data sent to a data transmission line 1 is to be sent to a data transmission line, e.g., 100, to an identifier decoding section 3. An identifier decoding section 3 decodes an identifier sent from the identifier transmission line 2, a control signal 10c is given to the control section 10, which is activated and the data sent from the data transmission line 1 is sent to the transmission line 100. Conversely, when the identifier representing that the data is to be sent from the identifier transmission line 2 to a data transmission line 200, the identifier decoding section 3 gives a control signal 20c to the control section 20, which is activated and the data sent to the data transmission line 1 is sent to the data transmission line 200.

9. 发明专利

JPS629449A DATA TRANSMITTER 失效
公开(公告)号：JPS629449A
公开(公告)日：1987-01-17
申请号：JP14859485
申请日：1985-07-05
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI
IPC分类号： H04L13/08 , G06F5/06 , G06F13/00 , G06F13/36 , G06F15/16 , G06F15/167 , G06F15/80 , G06F15/82 , G11C19/28
摘要： PURPOSE:To increase the data conflux operation speed without blocking the data flow by permitting th conflux of data when a primary line has an idle state and the arrival of the final word is detected at a prescribed position of a conflux data transmission line. CONSTITUTION:When no data exists on a primary line, the output to an idle buffer monitor part is set at '1'. Then a node A is set at '1' when the head of a packet reaches a conflux data transmission line 70. However the conflux of data is not permitted yet. The output of an OR gate 90 is set at '1' when a node G is set at '1' after the final word of a conflux packet reaches a data latch 71b. As a result, the inputs of an AND gate 63 are all set at '1' together with its output set also at '1'. Thus a flip-flop 94b is set and the input given to a 4-input NAND gate 66 from the flip-flop 64b is set at '1' against the line 70. At the same time, a data latch 61b is set under an output enable state. Then the packet on the line 70 is added to the primary line.

10. 发明专利

JPS61262958A DATA TRANSMITTING DEVICE 失效
公开(公告)号：JPS61262958A
公开(公告)日：1986-11-20
申请号：JP10667285
申请日：1985-05-17
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , KOMORI NOBUFUMI , SHIMA KENJI
IPC分类号： G06F5/06 , G06F13/00 , G06F13/36 , G06F13/38 , G06F15/16 , G06F15/177 , G06F15/82
摘要： PURPOSE:To improve the flexibility of a branch processing by providing a branching condition generating means has plural branching conditions and designating one of these conditions in response to the contents of the data on an input data transmission line to give the designated conditions to a branch deciding means. CONSTITUTION:When data are supplied to an input data transmission line 11, one of plural branching conditions is selected and designated at a branching condition generating part 16 in response to the contents of the data. This branching conditions is supplied to a branch deciding part 15 where the input branching conditions is compared with the conditions of the data. When the coincidence is obtained between both conditions, a branch control part 14 gives the data on a transmission line 11 to a branch data transmission line 13. While this data is given to an output data transmission line 12 when no coincidence is obtained between both conditions. Thus the branching conditions can be changed in accordance with an operation mode. Then the flexibility of the branch processing is improved.

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