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1. 发明专利

JPH0887475A INFORMATION PROCESSOR AND COMPUTING METHOD THEREIN 失效
公开(公告)号：JPH0887475A
公开(公告)日：1996-04-02
申请号：JP18019595
申请日：1995-07-17
申请人： MITSUBISHI ELECTRIC CORP
发明人： OSHIMA JOJI , TAMURA TOSHIYUKI , KOTO SATORU , TSUBOTA HIRONO , KOMORI NOBUFUMI , NAKAJIMA SHINJI , TERADA HIRONORI , IWATA MAKOTO , YAMAGUCHI KATSUTO , ONISHI JUNJI , KONDO AKIRA
IPC分类号： G06F15/173 , G06F15/80 , G06F15/82 , G06F17/13 , G06F15/16
摘要： PURPOSE: To shorten the communication time between element processors and speed up the processing by performing computation by placing element processors in operation independently and asynchronously by using data trans ferred by plural data buses. CONSTITUTION: The respective element processors 3 are connected with one another through inter-element-processor connections 7, initial conditions and border conditions are set according to control instructions sent from a host computer 1 to the information processor 2 through a network 4, and computation results are sent out. Then each element processor, consisting of a processing unit 5 and a memory part 6, stores the memory part 6 with the initial conditions and border conditions sent from the host computer 1 through the network 4 and inter-element-processor connections 7, performs arithmetic processing independently by the processing unit 5 after receiving a computation start token from the host computer 1, and writes the data after the processing in the memory part 6.

2. 发明专利

JPH06120777A DISTRIBUTED PROCESSING DEVICE FOR DIGITAL FILTER 失效
公开(公告)号：JPH06120777A
公开(公告)日：1994-04-28
申请号：JP27166892
申请日：1992-10-09
申请人： TERADA HIRONORI , MITSUBISHI ELECTRIC CORP , SHARP KK
发明人： TERADA HIRONORI , IWATA MAKOTO , MIZUNO MASAYUKI
IPC分类号： H03H17/00 , G06F17/00 , H03H17/02 , H04N1/40
摘要： PURPOSE:To reduce the input flow rate to each digital filter by preliminarily classifying input signal data to two-dimensional digital filters based on a certain rule and subjecting input signal data groups after classification to digital filtering independently of one another. CONSTITUTION:Inputted signal data are preliminarily classified based on the certain rule by a signal data classifying means 31 to preliminarily reduce the data input rate. Classified signal data are given to a filtering means 32 and are subjected to digital filter processings independent of one another, thereby raising the data input rate for the whole, namely, the sampling frequency.

3. 发明专利

JPH0564381B2 失效
公开(公告)号：JPH0564381B2
公开(公告)日：1993-09-14
申请号：JP1754486
申请日：1986-01-28
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F13/20 , G06F13/36 , G06F15/82

4. 发明专利

JPH0475133A PROGRAM DEVELOPING DEVICE 失效
公开(公告)号：JPH0475133A
公开(公告)日：1992-03-10
申请号：JP19181890
申请日：1990-07-17
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , NISHIKAWA HIROAKI , YAMAZAKI TETSUO , INAOKA MIE , SHIMA KENJI , YOSHIDA SHINICHI , HINE TOSHIHARU , NISHIKAWA YOICHIRO , HARA HIDEJI
IPC分类号： G06F9/06
摘要： PURPOSE:To construct a software system with high quality by defining a software system multilaterally by enabling one piece of specification definition information(one function) to be described by using plural expression formats. CONSTITUTION:Graphic editors E1-En each of which is provided with a plotting and editing function according to different expression formats, and a main body device 1 which generates a program according to specification description supplied from a user are provided. The specification definition information to be supplied to object software is inputted by using the plural expression formats and also, in hierarchical manner, and an executable program can be generated from the specification definition information as preserving hierarchical property held by the specification definition information. In such a way, it is possible to express one specification definition by the plural expression formats, and to express one specification definition multilaterally, and to realize prototype environment with superior correspondence with the specification description.

5. 发明专利

JPS6368932A INFORMATION PROCESSOR 失效
公开(公告)号：JPS6368932A
公开(公告)日：1988-03-28
申请号：JP21361086
申请日：1986-09-10
申请人： MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP , SHARP KK
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , TOKURA TAKESHI , TAKAKURA MINORU , HARA HIDEJI , NISHIKAWA YOICHIRO , AKECHI MITSUO , OKAMOTO TOSHIYA , KOMATSU KOJI
IPC分类号： G06F15/82 , G06F9/44
摘要： PURPOSE:To perform proper input limitation by providing an input control part and sending external input data corresponding to an input permission token generated according to the execution of an input instruction to an information processor main body. CONSTITUTION:A processing element 1 equipped with the information processor main body 8, a network 6 in a processing element, etc., is provided with an input control part 8 which receives the external input data through the network 6. This control part 6 controls the external input data to the main body 8 by receiving the input permission token generated when the main body 8 executes an instruction indicated in the driving program of a program storage part 3 by an arithmetic part 5 for operand data passed from a queuing part 4. Therefore, input limitation is performed properly even for a program which varies in processed variable with an input data value to prevent the processor main body from stopping owing to an excessive input and the throughput from decreasing owing to the input limitation.

6. 发明专利

JPS6223254A DATA TRANSMISSION EQUIPMENT 失效
公开(公告)号：JPS6223254A
公开(公告)日：1987-01-31
申请号：JP16360585
申请日：1985-07-23
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , SHIMA KENJI , KOMORI NOBUFUMI
IPC分类号： G06F15/16 , G06F5/06 , G06F13/00 , G06F13/36 , G06F15/177 , G06F15/82
摘要： PURPOSE:To send a data through a desired transmission line even when a different kind of data is inputted by discriminating whether or not a transmission enable signal is outputted from plural parallel transmission lines and sending a data to any transmission line according to an identifier attended to the data of the plural transmission lines. CONSTITUTION:An identifier transmission line 2 gives an identifier representing that a data sent to a data transmission line 1 is to be sent to a data transmission line, e.g., 100, to an identifier decoding section 3. An identifier decoding section 3 decodes an identifier sent from the identifier transmission line 2, a control signal 10c is given to the control section 10, which is activated and the data sent from the data transmission line 1 is sent to the transmission line 100. Conversely, when the identifier representing that the data is to be sent from the identifier transmission line 2 to a data transmission line 200, the identifier decoding section 3 gives a control signal 20c to the control section 20, which is activated and the data sent to the data transmission line 1 is sent to the data transmission line 200.

7. 发明专利

JPS629449A DATA TRANSMITTER 失效
公开(公告)号：JPS629449A
公开(公告)日：1987-01-17
申请号：JP14859485
申请日：1985-07-05
申请人： MITSUBISHI ELECTRIC CORP , SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , SHIMA KENJI , KOMORI NOBUFUMI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI
IPC分类号： H04L13/08 , G06F5/06 , G06F13/00 , G06F13/36 , G06F15/16 , G06F15/167 , G06F15/80 , G06F15/82 , G11C19/28
摘要： PURPOSE:To increase the data conflux operation speed without blocking the data flow by permitting th conflux of data when a primary line has an idle state and the arrival of the final word is detected at a prescribed position of a conflux data transmission line. CONSTITUTION:When no data exists on a primary line, the output to an idle buffer monitor part is set at '1'. Then a node A is set at '1' when the head of a packet reaches a conflux data transmission line 70. However the conflux of data is not permitted yet. The output of an OR gate 90 is set at '1' when a node G is set at '1' after the final word of a conflux packet reaches a data latch 71b. As a result, the inputs of an AND gate 63 are all set at '1' together with its output set also at '1'. Thus a flip-flop 94b is set and the input given to a 4-input NAND gate 66 from the flip-flop 64b is set at '1' against the line 70. At the same time, a data latch 61b is set under an output enable state. Then the packet on the line 70 is added to the primary line.

8. 发明专利

JPS61262958A DATA TRANSMITTING DEVICE 失效
公开(公告)号：JPS61262958A
公开(公告)日：1986-11-20
申请号：JP10667285
申请日：1985-05-17
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , KOMORI NOBUFUMI , SHIMA KENJI
IPC分类号： G06F5/06 , G06F13/00 , G06F13/36 , G06F13/38 , G06F15/16 , G06F15/177 , G06F15/82
摘要： PURPOSE:To improve the flexibility of a branch processing by providing a branching condition generating means has plural branching conditions and designating one of these conditions in response to the contents of the data on an input data transmission line to give the designated conditions to a branch deciding means. CONSTITUTION:When data are supplied to an input data transmission line 11, one of plural branching conditions is selected and designated at a branching condition generating part 16 in response to the contents of the data. This branching conditions is supplied to a branch deciding part 15 where the input branching conditions is compared with the conditions of the data. When the coincidence is obtained between both conditions, a branch control part 14 gives the data on a transmission line 11 to a branch data transmission line 13. While this data is given to an output data transmission line 12 when no coincidence is obtained between both conditions. Thus the branching conditions can be changed in accordance with an operation mode. Then the flexibility of the branch processing is improved.

9. 发明专利

JPS61262923A ADVANCED CONTROL CIRCUIT FOR DATA PROCESSING CIRCUIT OF PIPELINE SYSTEM 失效
公开(公告)号：JPS61262923A
公开(公告)日：1986-11-20
申请号：JP10666985
申请日：1985-05-17
申请人： SHARP KK , MATSUSHITA ELECTRIC IND CO LTD , SANYO ELECTRIC CO , MITSUBISHI ELECTRIC CORP
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , MIYATA SOICHI , MATSUMOTO SATOSHI , ASANO HAJIME , SHIMIZU MASAHISA , MIURA HIROKI , KOMORI NOBUFUMI , SHIMA KENJI
IPC分类号： G06F7/00 , G06F9/44 , G06F13/00 , G06F15/82
摘要： PURPOSE:To control previously a prescribed byte line stage and to shortening the executing time with a single pipeline by performing the processing to decide the processing contents at a prescribed pipeline stage in parallel with execution of the pipeline processing. CONSTITUTION:An input data transmission line 100 of a data processor of a pipeline system consists of an asynchronous self-running shift register. The data on the line 100 are applied to a selective branch control part 400 to which the control signal of the branch conditions is supplied from a branch deciding part 500. This part 500 is used as an advanced control circuit to decide whether or not the data are branched simultaneously and in parallel with advance of the pipeline processing of the data on the line 100. The result of this decision is given to a control part 400. Based on this result of decision, the part 400 delivers the data on the line 100 to an output data transmission line 200 consisting of an asynchronous self-running shift register or a branch data transmission line 300. Thus the data transmitting time is shortened with a single pipeline.

10. 发明专利

JPS61110071A Simulation system and simulator for logical circuit 失效
标题翻译：逻辑电路仿真系统和仿真器
公开(公告)号：JPS61110071A
公开(公告)日：1986-05-28
申请号：JP23278384
申请日：1984-11-02
申请人： Matsushita Electric Ind Co Ltd , Mitsubishi Electric Corp , Sanyo Electric Co Ltd , Sharp Corp
发明人： TERADA HIRONORI , ASADA KATSUHIKO , NISHIKAWA HIROAKI , HARA HIDEJI , AKECHI MITSUO , OKAMOTO TOSHIYA , ASANO HAJIME
IPC分类号： G01R31/28 , G06F17/50 , G06F19/00
CPC分类号： G06F17/5022
摘要： PURPOSE: To achieve a higher speed of computation, by a method wherein input information of logical circuit components and a signal level are computed at each time of starting and ending the signal level and only when there are changes in the output signal level, the output signal level and the times of starting and ending it are applied sequentially to the components.
CONSTITUTION: With an AND gates of three inputs 1, 2 and 3, the outputs and computed separately at the time (a), (b), (c) and the like when input signals 1, 2 and 3 rise or fall. Only at times (c) and (d) when the outputs change, the output signal and times of starting and ending the level are sent out to logical circuit components, for example, gates such as AND, NAND, OR and NOR gates, buffers and FFs. In this manner, as an output is produced only when outputs of the components change, the number of packets flowing through the input processing section - output processing section - input processing section... can be reduce to the minimum necessary and as the computation is done only when the signal changes, the frequency of data processing can be cut drastically thereby achieving a higher speed of the simulation.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：为了实现更高的计算速度，通过一种方法，其中在开始和结束信号电平的每个时间仅计算逻辑电路分量的输入信息和信号电平，并且仅当输出信号电平有变化时，输出信号电平和开始和结束的时间顺序地应用于组件。构成：输入信号1,2和3的时间（a），（b），（c）等分别输入和输出三个输入1,2和3的“与”门。仅在时间（c）和（d）时，输出变化时，输出信号和开始和结束电平的时间被发送到逻辑电路部件，例如门，如AND，NAND，或和和门，缓冲器和FFs。以这种方式，由于仅当组件的输出改变时才产生输出，所以流经输入处理部分 - 输出处理部分 - 输入处理部分的分组数量可以减少到必要的最小值，并且计算是只有当信号变化时才能完成数据处理的频率，从而实现更高的仿真速度。

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