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11. 发明专利

JP2013048132A Solid-state image sensor 有权
标题翻译：固态图像传感器
公开(公告)号：JP2013048132A
公开(公告)日：2013-03-07
申请号：JP2011185464
申请日：2011-08-29
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： FURUKAWA TOMOYASU , SAKAI SATORU , NONAKA YUSUKE , SUGINO MASAYA
IPC分类号： H01L27/146 , H01L27/148
CPC分类号： H01L27/14689 , H01L27/14607 , H01L27/1461 , H01L27/1463 , H01L27/14645
摘要： PROBLEM TO BE SOLVED: To solve the following problem: In an area with poor internal electric field, optical charges generated within an area deeper than a photodiode PD scatter in a lateral direction, so that low sensitivity occur due to a flow of optical photoelectrons into adjacent pixels (crosstalk).SOLUTION: A crosstalk prevention layer DNW 9 is formed at a photodiode PD formation section and between a pixel and a peripheral circuit, thereby to reduce crosstalk between pixels or between a pixel region and a peripheral circuit region and improve photosensitivity.
摘要翻译：要解决的问题：解决以下问题：在内部电场差的区域中，在比光电二极管PD更深的区域内产生的光电荷沿横向散射，从而由于流动而产生低灵敏度光电子进入相邻像素（串扰）。解决方案：在光电二极管PD形成部分和像素与外围电路之间形成串扰防止层DNW 9，从而减少像素之间或像素区域与外围电路区域之间的串扰，并提高光敏性。版权所有（C）2013，JPO＆INPIT

12. 发明专利

JP2003273240A Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2003273240A
公开(公告)日：2003-09-26
申请号：JP2002076182
申请日：2002-03-19
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： HACHIMINE SEITA , SHIMIZU AKIHIRO , OOKI NAGATOSHI , SAKAI SATORU , YAMAMOTO NAOKI
IPC分类号： H01L29/78 , H01L21/336 , H01L21/8238 , H01L27/092
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823828 , H01L29/665 , H01L29/785 , H01L29/78642 , H01L29/78645
摘要： PROBLEM TO BE SOLVED: To increase drain currents (to improve current drivability) of an n-type FET and a p-type FET. SOLUTION: The method of manufacturing the semiconductor device having the n-type and p-type FETs formed on a semiconductor wafer has: a process (a) for generating tensile stress in the channel formation area of the n-type FET to cover gate electrodes of the p-type FET on the n-type and p-type FETs in a state of covering a semiconductor area with an insulating film between the gate electrodes and the element separation area of the semiconductor wafer; a process (b) for selectively removing the first insulating film on the p-type FET by applying etching treatment; a process (c) for forming a second insulating film for generating compression stress in the channel formation area of the p-type FET to cover the gate electrodes on the n-type and p-type FETs; and a process (d) for selectively removing the second insulating film on the n-type FET. COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：为了增加n型FET和p型FET的漏极电流（以提高电流驱动能力）。解决方案：制造具有形成在半导体晶片上的n型和p型FET的半导体器件的方法具有：在n型FET的沟道形成区域中产生拉伸应力的工序（a）在栅电极和半导体晶片的元件分离区域之间以绝缘膜覆盖半导体区域的状态下，n型和p型FET上的p型FET的覆盖栅极电极; 用于通过施加蚀刻处理来选择性地去除p型FET上的第一绝缘膜的工艺（b）; 一种用于在p型FET的沟道形成区域中形成用于产生压应力的第二绝缘膜以覆盖n型和p型FET上的栅电极的工艺（c）; 以及用于选择性地去除n型FET上的第二绝缘膜的工艺（d）。版权所有（C）2003，JPO

13. 发明专利

JP2001015612A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JP2001015612A
公开(公告)日：2001-01-19
申请号：JP22599199
申请日：1999-08-10
申请人： HITACHI LTD
发明人： KANDA TAKAYUKI , HIRAIWA ATSUSHI , SUZUKI NORIO , SAKAI SATORU , IKEDA SHUJI , YOSHIDA YASUKO , HORIBE SHINICHI
IPC分类号： H01L21/8234 , H01L21/316 , H01L21/8238 , H01L27/088 , H01L27/092
摘要： PROBLEM TO BE SOLVED: To provide a technology capable of improving the reliability of a semiconductor integrated circuit device having two or more kinds of gate insulating films each different in thickness. SOLUTION: A silicon oxide film 7 is formed on a silicon oxide film 6 which is formed on the surface of a semiconductor substrate 1. Then, using a photoresist pattern 8 covering a region A for forming a thick gate insulating film as a mask, the films 6 and 7 in a region B for forming a thin gate insulating film are removed, after which the pattern 8 and the film 7 are removed. Successively, the substrate 1 is thermally oxidized to form gate insulating films each having a different thickness.

14. 发明专利

JPH09320982A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING DEVICE THEREOF 失效
公开(公告)号：JPH09320982A
公开(公告)日：1997-12-12
申请号：JP13604696
申请日：1996-05-30
申请人： HITACHI LTD , TEXAS INSTRUMENTS JAPAN
发明人： IKEDA YOSHIHIRO , SAKAI SATORU , OGASAWARA MAKOTO , SATO KAZUO , KAERIYAMA TOSHIYUKI , MATSUNAGA KATSUTOSHI , MATSUI TAKESHI
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/43 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a technique which improves reliability of an MISFET comprising a gate electrode of a tungsten polycide film. SOLUTION: An n-type impurity for forming an n-type semiconductor region 7 is doped into a semiconductor substrate 1 with a gate electrode 6, comprising a WSix (tungsten polycide) film 5 and a polycrystalline silicon film 4, as a mask. Next, the semiconductor substrate 1 is cleaned using liquid which does not etch silicon oxide or silicon oxidizable liquid, and immediately after the exposed surface of the WSix film 5 is covered with a thin natural oxide film 8, heat processing at a temperature of 900 deg.C is performed on the semiconductor substrate 1 for activating the n-type impurity. This processing causes composition change in the WSix film 5, however, as the extraction of W or WSi is suppressed by the natural oxide film 8, short circuit between adjacent gate electrodes can be prevented.

15. 发明专利

JPH09246405A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND ITS MANUFACTURING METHOD 失效
公开(公告)号：JPH09246405A
公开(公告)日：1997-09-19
申请号：JP4939396
申请日：1996-03-07
申请人： HITACHI LTD
发明人： KASHU NOBUYOSHI , SAKAI SATORU
IPC分类号： H01L21/8247 , H01L21/20 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To notably cut down the defect development probability such as defective retention even if fine structural defect exists in an oxide film in a charge storage non-volatile memory. SOLUTION: A floating gate electode 7 is divided into electrically divided numerous insular particles 6 so that the charge amount Qi accumulated in respective regions i may be in sufficiently less value than the required charge amount Q corresponding to cell data judgment. Furthermore, the total sum ΣQi of said charge amount Qi stored in area i is specified to be almost equivalent to the required charge amount Q and said charge amount Qi to be equivalent to the change amount ΔQ of allowable holding charge in the data holding time or satisfying the following inequality of (Qi

16. 发明专利

JPH06326045A TEMPERATURE CONTROLLER IN SEMICONDUCTOR MANUFACTURING DEVICE 失效
公开(公告)号：JPH06326045A
公开(公告)日：1994-11-25
申请号：JP13537893
申请日：1993-05-13
申请人： KOKUSAI ELECTRIC CO LTD , HITACHI LTD
发明人： TOMITA MASAYUKI , IKEDA FUMIHIDE , SAKAI SATORU , KASHU NOBUYOSHI
IPC分类号： C23C16/52 , F27D19/00 , H01L21/205 , H01L21/22 , H01L21/31 , H01L21/324
摘要： PURPOSE:To provide a temperature controller enabling a temperature rise at high speed and enabling control at high speed in a semiconductor production device requiring temperature control. CONSTITUTION:Heating elements 6, 7, 9, 10, 11, 12, 13, 14, temperature controllers 31, 32, 33, 34 driving and controlling the heating elements, and heating temperature detectors 36, 37, 38, 39 detecting the heating temperatures of the heating elements are provided. A target value input to the temperature controllers and the result of detection from the heating temperature detectors are compared, and the temperatures of the heating elements are controlled while the heating elements are used as heaters, in which conductive films are evaporated on ceramic boards. The heating temperature detectors are employed as optical fiber sensors, the temperature rising performance of the heaters is improved, and the detection speed of the heating temperature detectors is enhanced.

17. 发明专利

JP2011040647A Solid-state imaging device 审中-公开
标题翻译：固态成像装置
公开(公告)号：JP2011040647A
公开(公告)日：2011-02-24
申请号：JP2009188189
申请日：2009-08-17
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： SUGINO MASAYA , SAKAI SATORU , NONAKA YUSUKE , SAITO TOMOHIRO , FURUKAWA TOMOYASU , HAYASHI HIROYUKI
IPC分类号： H01L27/14 , H01L27/146 , H04N5/335
CPC分类号： H01L27/14605 , H01L27/14623 , H01L27/14627 , H01L27/1463 , H01L27/14636 , H01L2924/0002 , H01L2924/00
摘要： PROBLEM TO BE SOLVED: To improve light collection efficiency of a solid-state imaging device using a microlens to focus light onto a light-receiving region with the wiring pattern of the solid-state imaging device. SOLUTION: The solid-state imaging device has a first wiring layer 19 and a second wiring layer 22 each formed in a ring shape so as to trace the outline of the light-receiving region of a photodiode PD, and thereby all of the first wiring layer 19, the second wiring layer 22 and a third wiring layer 25 are arranged to surround an upper part of the photodiode PD. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：为了提高使用微透镜的固态成像装置的光收集效率，以将固体成像装置的布线图案将光聚焦到光接收区域上。解决方案：固态成像装置具有形成为环状的第一布线层19和第二布线层22，以便跟踪光电二极管PD的光接收区域的轮廓，从而全部第一布线层19，第二布线层22和第三布线层25布置成围绕光电二极管PD的上部。版权所有（C）2011，JPO＆INPIT

18. 发明专利

JP2001044292A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JP2001044292A
公开(公告)日：2001-02-16
申请号：JP21173599
申请日：1999-07-27
申请人： HITACHI LTD
发明人： HIRAIWA ATSUSHI , SUZUKI NORIO , KANDA TAKAYUKI , KAWAMURA MASAO , SAKAI SATORU
IPC分类号： H01L21/8234 , H01L21/316 , H01L21/8242 , H01L27/088 , H01L27/10 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To reduce a defect in gate insulation by forming a gate insulation film with different thickness on a semiconductor substrate where COP, dislocation, and an oxidation induction lamination layer defective region do not exist when viewed from element characteristics. SOLUTION: N wells 13NW1 and 13NW2, and P wells 13PW1 and 13PW2 are formed at the main surface side of a semiconductor substrate 1s. A shallow- grooved separation part 14 is formed on the main surface of the semiconductor substrate 1s. In the separation part 14, an insulation film 14b for separation made of a silicon oxide film or the like is buried into a shallow groove 14a being made in the thickness direction of the semiconductor substrate 1s for formation. Then, first and second gate insulation films 16i1 and 16i2 are formed on an entire surface excluding the separation groove 14, and the thickness of the first gate insulation film 161 is set layer than that of the second gate insulation film 16i2.

19. 发明专利

JP2003297947A Semiconductor integrated circuit device and its manufacturing method 审中-公开
标题翻译：半导体集成电路设备及其制造方法
公开(公告)号：JP2003297947A
公开(公告)日：2003-10-17
申请号：JP2002098996
申请日：2002-04-01
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： YAMAMOTO TOMOSHI , FURUKAWA RYOICHI , SAKAI SATORU
IPC分类号： H01L21/28 , H01L21/3205 , H01L21/768 , H01L21/8234 , H01L21/8238 , H01L23/52 , H01L27/088 , H01L27/092 , H01L29/423 , H01L29/49
摘要： PROBLEM TO BE SOLVED: To improve characteristics of a semiconductor integrated circuit device by reducing contaminant caused by a high dielectric film consisting of a metallic oxide.
SOLUTION: An Al
2 O
3 film 8a is formed as a gate insulation film on a p-type well 3 and an n-type well 4 of a semiconductor substrate 1 by a thermal CVD method. In the process, after a silicon oxide film 29 is formed on an Al
2 O
3 film 8b, which is formed in a rear of the semiconductor substrate 1 and made an upper surface, a gate electrode G consisting of a polycrystalline silicon film 9a, a WN film (not illustrated) and a W film 9b is formed on the film 8a. An n
+ type semiconductor region 14 and a p
+ type semiconductor region 15 (source, drain) are formed in both sides of the gate electrode G. Since the film 8b of a rear of the semiconductor substrate 1 is covered with a silicon oxide film 29 in this way, it is possible to prevent an inside of a device from being contaminated by a metal or a metallic compound when a rear of the semiconductor substrate 1 comes into contact with a stage of a manufacturing device.
COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：通过减少由金属氧化物组成的高介电膜引起的污染物来改善半导体集成电路器件的特性。解决方案：在半导体的p型阱3和n型阱4上形成作为栅极绝缘膜的Al 3 SB 3 O 3 / 基板1通过热CVD法。在该过程中，在形成在半导体衬底1的后部并形成上部的Al 2 O 3 SB 3膜8b上形成氧化硅膜29之后，在膜8a上形成由多晶硅膜9a，WN膜（未示出）和W膜9b构成的栅极电极G. 在栅极电极G的两侧形成有n + SP + + / SP型半导体区域14和ap

20. 发明专利

JPH11317458A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH11317458A
公开(公告)日：1999-11-16
申请号：JP12436598
申请日：1998-05-07
申请人： HITACHI LTD
发明人： HIRAIWA ATSUSHI , OJI YUZURU , SAKUMA KAZUKI , SUZUKI NORIO , KANDA TAKAYUKI , TAKAHASHI KENJI , SHIMIZU HIROBUMI , SAKAI SATORU
IPC分类号： H01L21/336 , H01L21/8234 , H01L27/088 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce the occurrences of defects in a gate insulating film by forming gate insulating films, having different thicknesses on a single-crystal semiconductor layer after the semiconductor layer is formed on a semiconductor substrate by the epitaxial method. SOLUTION: After a single-crystal semiconductor layer 1e is formed on a semiconductor substrate 1s by the epitaxial method without through an element forming process, gate insulating films 16i1 and 16i2 having relatively different thicknesses are formed on the epitaxial layer 1e containing very few crystal defects. Consequently, the occurrences of the defects in the gate insulating film 16i1 can be reduced in the forming process of the gate insulating films 16i1 and 16i2. Thus the decomposition of a defect in the gate insulating film 16i1 into such a serious defect that causes insulation breakdown of the insulating film 16i1 can be suppressed, in the course of cleaning treatment which is performed before second gate oxidation in the process of forming the two kinds of gate insulating films. Therefore, the possibility of the gate insulating films 16i1 and 16i2 causing insulation breakdown can be reduced.

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