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11. 发明专利

JPS60261224A PARITY ALLOWING SYSTEM 失效
公开(公告)号：JPS60261224A
公开(公告)日：1985-12-24
申请号：JP11641984
申请日：1984-06-08
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEMURA TETSUO , NISHIMURA KAZUO , TOKUSHIMA TAKASHI
IPC分类号： H03M9/00 , H03M13/00
摘要： PURPOSE:To add simple hardware irrespective of the value of bit length, enabling generation of parity and improve performance by detecting faults of a series parallel converting element. CONSTITUTION:Series data that make n bit length near the lead 101 of a parity allowing system a frame unit is stored successively in a shift register 1 by a clock 103. FF is cleared by clock 102 of the head of each frame, and the value of exclusive logical sum output prepared by a gate 2 by output 105 and series data is accumulated in clock 103 by FF3. When data for one frame are stored in the register 1, even number parity for data D1-Dn of relevant frame is generated in FF3. Then, parallel data 106-1-106-n and parity 105 are set in a register 5 by a frame clock 104. Thus, generation of parity is made possible by simple constitution, and capacity of the system is improved.

12. 发明专利

JPS60181862A SETTING SYSTEM OF DMA TRANSFER BUFFER 失效
公开(公告)号：JPS60181862A
公开(公告)日：1985-09-17
申请号：JP3606784
申请日：1984-02-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , GOUHARA SHINOBU , TAKAHASHI TATSUROU , ARAGAKI NAOYA , IWASE YASUMASA
IPC分类号： G06F13/28 , G06F13/38
摘要： PURPOSE:To shorten the time from generation of a DMA transfer start request to start of DMA transfer by reading out directly empty buffer designating information without passing a main controller when the DMA transfer start request is generated and setting this information in a device itself. CONSTITUTION:When a buffer 31-i of a main storage device 3 becomes empty, a main controller 2 reads out the write address in a buffer designating queue 32 in accordance with a write address pointer 41. A start address Ai of the empty buffer is written in the buffer designating queue 32 in accordance with this read address, and thereafter, the write address is updated and is written in the write address pointer. When receiving a DMA transfer start request signal from a data receiving device 6, a DMA controller 5 reads out the read address in the buffer designating queue 32 in accordance with a read address pointer 42 and reads out directly the start address (for example, Aj) of the buffer in accordance with the readout address by DMA transfer and sets it in the device 5 itself. Thereafter, the read address is updated and is written in the read address pointer.

13. 发明专利

JPS6268356A INPUT CONFIRMING SYSTEM 失效
公开(公告)号：JPS6268356A
公开(公告)日：1987-03-28
申请号：JP20653985
申请日：1985-09-20
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , GOHARA SHINOBU , SAKAI YOICHI , SHINOOKA MAKOTO , KOIKE HIDEYUKI
IPC分类号： H04M3/42
摘要： PURPOSE:To confirm the inputted information in the unit of blocks by sending a voice corresponding to the received character string at each section of blocks to the character string inputted from the user. CONSTITUTION:In order to designate a facsimile confidential communication, '1' is dialed at first according to the numbering system. The number is received by a PB reception circuit 46 connected to the operating talking line in an IRE 4 and when a controller 42 receives the notice, the circuit 46 receives the dial number, then number system information stored in a storage device 43 is read and referenced, recognized and held. Succeedingly, when a dial number 2 is received by the PB reception circuit 46, the end of reception of a block being a communication identification code is recognized, a voice signal corresponding to a dial number 12 is read sequentially from a voice buffer circuit 44 and sent to the user 1 as a voice (a) via a voice transmission circuit 45. The user 1 listens to the voice to confirm the correct input.

14. 发明专利

JPS60183666A DMA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS60183666A
公开(公告)日：1985-09-19
申请号：JP3856784
申请日：1984-03-02
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TAKEMURA TETSUO , IWAKI SHINICHI , SHIMIZU KOUICHI , TAKAHASHI TATSUROU , ARAGAKI NAOYA , IWASE YASUMASA
IPC分类号： G06F13/28
摘要： PURPOSE:To accommodate lots of I/O devices and also to attain miniaturization and economy of the device by providing a transfer request cue storing a transfer request from each I/O and a data register storing temporarily a transfer data. CONSTITUTION:The transfer request cue 8 storing the transfer request from each I/O and the data register 3 storing temporarily the transfer data corresponding to each I/O are provided to a direct memory access DMA controller 2 (DMAC2). When the I/O 1-2 generates a request, the I/O 1-2 gives a transfer request to a signal line 104. When a permission signal is outputted from a control circuit 13 according to the request signal, a data is written in the register 3 and the device number is written in the cue 8. Then the data in the register 3 is transferred according to the transfer request stored in the cue 8 by the control of the circuit 13. Lots of the I/O devices are attained by providing the transfer request cue 8 and the data register 3 in this way and the miniaturization and economy of the device are attained.

15. 发明专利

JPS60183665A DMA TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPS60183665A
公开(公告)日：1985-09-19
申请号：JP3856684
申请日：1984-03-02
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , SHIMIZU KOUICHI , TAKAHASHI TATSUROU , ARAGAKI NAOYA , IWASE YASUMASA
IPC分类号： G06F13/28
摘要： PURPOSE:To set a proper number of buffers to the system by providing an idle buffer management means and a buffer setting means or the like so as to use a reception buffer group on a main storage device by lots of signal sources in common thereby attaining efficient operation. CONSTITUTION:A reception buffer group 41 on the main storage device 4 is n-set of buffer groups storing data of the device 4 and provided in common to plural signal sources 1-1-1-m respectively. A CPU3 gives a head address of a buffer 41-i to the idle buffer management cue 6 via a CC bus 8 when the buffer 41-i is idle. When a signal line 1-2 starts reception next, the buffer setting is requested to a buffer setting circuit 5. The circuit 5 reads the head address of the idle buffer by using the cue 6 in the order of reception of the request and writes it to an address register corresponding to a line 1-2 in a DMA controller 2. Since the buffer group is used in common by lots of signal sources, the buffer group is operated efficiently and the number of buffers optimum to the system is set.

16. 发明专利

JPH01213049A FAULT STATISTICS SYSTEM FOR COMMUNICATION CONTROL UNIT 失效
公开(公告)号：JPH01213049A
公开(公告)日：1989-08-25
申请号：JP3739588
申请日：1988-02-22
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KIMURA KENICHI , TAKEMURA TETSUO , KUNIMOTO MASAO , KAWAKITA KENJI , TASHIRO TOKUO
IPC分类号： H04L29/14 , H04L13/00
摘要： PURPOSE:To make a fault information storage area to be small capacity and to accelerate trouble statistics processing by analyzing an occurring fault and making only the fault cause of a circuit specified from a host among the fault cause occurring to logic circuits as an object to be tabulated. CONSTITUTION:A microprocessor (MPU) 1 steps a physical trouble fault 52 at every fault cause every time when a physical circuit fault is informed from a circuit interface part 3 through a bus 8. On the other hand, it zero-clears a logic circuit fault counter 53 when it receives a monitoring link setting command through the high-order system interface part 4 and the bus 8 and registers link identification information among the command to a monitoring information identification area 50. At the step follow of the counter 53 after receiving the command, control link identification information is extracted from the address field 101 of a reception frame and set to a control link identification area 51. Next, procedure processing is executed and the contents of the areas 50 and 51 are compared when a procedure error exists. When the contents of them coincide each other, the corresponding fault counter is stepped. Therefore, the contents is tabulated on the counter 53.

17. 发明专利

JPS63209246A RECEIVING BUFFER ASSIGNING SYSTEM 失效
公开(公告)号：JPS63209246A
公开(公告)日：1988-08-30
申请号：JP4033487
申请日：1987-02-25
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： MORI MAKOTO , TAKEMURA TETSUO , SUZUKI TOSHIAKI , TAKAMURA HIDEO
IPC分类号： H04Q11/04
摘要： PURPOSE:To prevent the influence of a convergence to the inclination of a traffic between data having different high order layer control by classifying plural links into two groups or above and providing a data receiving buffer for a line control device and for a group in a processing device. CONSTITUTION:Receiving buffers 311, 312, 3n1 and 3n2 in a processing device are assigned to a line control device unit and a service access point unit. Thus, by assigning the receiving buffers 311, 312, 3n1 and 3n2 in the processing device to the line control device unit and the service access point unit, line control devices 11,..., 1n use the assigned receiving buffer, and therefore, the receiving buffer hunting competition with other line control device does not occur. Since the receiving buffer is assigned to a service access point unit, the straddle of different high order layer control parts 41 and 4n at the time of reading the data in the receiving buffer is not needed.

18. 发明专利

JPS60127842A MULTI-POINT ACCESS TERMINAL CONTROL SYSTEM 失效
公开(公告)号：JPS60127842A
公开(公告)日：1985-07-08
申请号：JP23549583
申请日：1983-12-14
申请人： NIPPON TELEGRAPH & TELEPHONE , HITACHI LTD
发明人： DOBASHI TADAHIKO , SHIMIZU KOUICHI , TAKEMURA TETSUO
IPC分类号： H04L12/28
摘要： PURPOSE:To attain common channel access with multi-point constitution by using a common channel access control circuit added to a data transmission/reception circuit to control the signal transmission to the common channel. CONSTITUTION:A data transmission request is given to a line idle detecting circuit 4 by allowing a transmission control circuit 13 to detect a flag pattern of a matcher 10. When a line is idle, a data transmission permission is given to the transmission control circuit 13. Since the control circuit 13 gives no command of transmission stand-by to a transmission/reception circuit 8, the clock supply to the data transmission/reception circuit 8 is conducted and data is transmitted. When the line is busy, since the data transmission permission is not given to the transmission control circuit 13, the transmission control circuit 13 gives a command of transmission stand-by to allow the data transmission/reception circuit 8 to stop the supply of an external clock to an external clock supply terminal TXC thereby stopping the succeeding data.

19. 发明专利

JPH0644258B2 失效
公开(公告)号：JPH0644258B2
公开(公告)日：1994-06-08
申请号：JP3606784
申请日：1984-02-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： IWAKI SHINICHI , TAKEMURA TETSUO , GOUHARA SHINOBU , TAKAHASHI TATSUROU , ARAGAKI NAOYA , IWASE YASUMASA
IPC分类号： G06F13/28 , G06F13/38

20. 发明专利

JPH02274038A NETWORK SERVICE OFFERING METHOD 失效
公开(公告)号：JPH02274038A
公开(公告)日：1990-11-08
申请号：JP9511689
申请日：1989-04-17
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： YOSHIE TATSUO , TAKEMURA TETSUO , FUKUSHIMA YUTAKA , SATO FUMITO
IPC分类号： G06F9/46 , H04L29/06 , H04Q3/00
摘要： PURPOSE:To flexibly cope with the addition and the change of a module by sharing an information managing means without providing a mans by which a transmission side module separately and independently manages information of the other module. CONSTITUTION:When the necessity for offering the service is generated by an information offer from other modules 101, 102 and a control from other modules 101, 102, the transmission side module 100 sends out a service offer request, for instance, a request packet by a broadcast format other modules 101 (102) without specifying the physical address of other modules 101 (102). Consequently, each module 101 (102) receives the request packet, but when its request contents are those of its own module, each module 101 (102) returns a response, executes an information offer to the transmission origin module 100, and executes the control of the transmission origin module 100. By executing a response processing to the request packet in such a manner a network service can be offered, while executing the communication between respective modules. Accordingly, it is possible to flexibly cope with the addition and the change of the other module.

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