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11. 发明专利

JPS59162679A Pulse driving detecting circuit 失效
标题翻译：脉冲驱动检测电路
公开(公告)号：JPS59162679A
公开(公告)日：1984-09-13
申请号：JP3453483
申请日：1983-03-04
申请人： Hitachi Ltd
发明人： TOYOOKA TAKASHI , AOKI HIROKAZU , SUGITA KEN
IPC分类号： G11C11/14
CPC分类号： G11C11/14
摘要： PURPOSE:To enable stable signal processing even in the presence of variance in pulse voltage by detecting the pulse voltage amplitude generated on both ends of a detecting line and adding a circuit that generates optimum clamp voltage according to the pulse voltage. CONSTITUTION:A clamp voltage circuit 24 that detects the pulse voltage amplitude of a main or dummy detecting line and prescribes clamp level voltage corresponding to the amplitude is added to a sense circuit. Rd represents the resistance of detecting lines 3, 4, Id represents the pulse voltage amplitude, Vd represents the voltage drop of diodes 18, 19 and Vbe represents the voltage drop between base and emitter of transistors 20, 21. At this time, the output voltage Ecp of a clamp voltage generating circuit 24 may be made to a value given by the following equation so as to make the pulse voltage amplitude applied to input of a differential amplifier 10 to 0.5V. Ecp=RdId-Vd-Vbe-0.5 When Vd is 0.7V and Vbe is 0.8V, it is enough for the Ecp to have a function to set a value lower than detecting line pulse voltage amplitude RdId by 2V.
摘要翻译：目的：通过检测检测线两端产生的脉冲电压振幅，并根据脉冲电压加上产生最佳钳位电压的电路，即使存在脉冲电压差异也能实现稳定的信号处理。构成：检测主或虚拟检测线的脉冲电压幅度并规定与振幅对应的钳位电平电压的钳位电压电路24被加到感测电路上。 Rd表示检测线3,4的电阻，Id表示脉冲电压幅度，Vd表示二极管18,19的电压降，Vbe表示晶体管20,21的基极和发射极之间的电压降。此时，输出可以使钳位电压产生电路24的电压Ecp为由下式给出的值，以便使得对差分放大器10的输入施加的脉冲电压振幅为0.5V。 Ecp = RdId-Vd-Vbe-0.5当Vd为0.7V且Vbe为0.8V时，Ecp具有将检测线脉冲电压振幅RdId低于2V的值的功能。

12. 发明专利

JPS59135685A Sense circuit for detecting pulse drive 失效
标题翻译：用于检测脉冲驱动的感测电路
公开(公告)号：JPS59135685A
公开(公告)日：1984-08-03
申请号：JP872083
申请日：1983-01-24
申请人： Hitachi Ltd
发明人： TOYOOKA TAKASHI , AOKI HIROKAZU , SUGITA KEN
IPC分类号： G11C11/14
CPC分类号： G11C11/14
摘要： PURPOSE:To form a sense circuit capable of performing stable operation by providing a level clamp circuit and a DC regenerating circuit between a bubble memory detector and an amplifying and signal comparison circuit to prevent the saturation of a differential amplifier and the fluctuation in a DC level of an output signal. CONSTITUTION:The output level fluctuation of a detecting signal is reduced by using a circuit where a DC regenerating circuit comprising coupling capacitors 30, 31 and transistors (TRs) 32, 33 and 34, 35 is added to a pulse drive sense circuit including a level clamp circuit. A DC reproducing control signal 36 is applied to based of the TRs 32, 33. A DC level of an output obtained at emitters of the TRs 25, 26 in this circuit is eliminated by the capacitors 30, 31, and transient response due to a pulse voltage due to capacitor coupling is decreased by the TRs 32, 33.
摘要翻译：目的：通过在气泡存储检测器和放大信号比较电路之间设置电平钳位电路和直流再生电路，形成能够进行稳定运行的检测电路，以防止差分放大器的饱和和直流电平的波动的输出信号。构成：通过使用包括耦合电容器30,31和晶体管（TRs）32,33和34,35的DC再生电路被添加到包括电平的脉冲驱动检测电路的电路来减小检测信号的输出电平波动钳位电路。直流再现控制信号36被施加到TR32,33的基础上。在该电路中的TR 25,26的发射极处获得的输出的直流电平由电容器30,31消除，并且由于电容耦合引起的脉冲电压由TRs32,33减小。

13. 发明专利

JPS59104782A Magnetic bubble memory device 失效
标题翻译：磁性气泡存储器件
公开(公告)号：JPS59104782A
公开(公告)日：1984-06-16
申请号：JP21142882
申请日：1982-12-03
申请人： Hitachi Ltd
发明人： SEKIGUCHI YOSHIHIRO , YOSHIDA KAZUTOSHI , CHIBA SHINSAKU , SUGIE MAMORU , AOKI HIROKAZU
IPC分类号： G11C11/14 , G11C19/08 , G11C29/00
CPC分类号： G11C29/86 , G11C19/0875
摘要： PURPOSE: To attain storage of the defect information, etc. even in case the number of minor loops is larger than or equal to the number of bits within an information storing minor loop, by increasing the number of bits of a map loop more than the number of bits of said minor loop.
CONSTITUTION: The number of bits within a map loop 2 is set triple as much as the number of bits within a minor loop 1. Therefore addresses A
2 and A
3 of the loop 2 are set at the same position as an address A
1 on the loop 1 even though the addresses A
2 and A
3 are at the position of the address A
1 on the loop 2. In other words, the A
1 of the loop 1 overlaps each of fields F
1 WF
3 of the loop 2. Therefore the A
1 of the loop 1 is recognized on the basis of the address A
1 , A
2 or A
3 of the loop 2 with synchronism with the A
1 of the loop 1. Thus the control is possible for a magnetic bubble memory element. It is also possible to set the number of bits within the loop 2 at the value ≥2 integer times as much as the number of bits within the loop 2.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：为了获得缺陷信息的存储，即使在小循环的数量大于或等于存储次要循环的信息中的位数的情况下，通过增加映射循环的比特数大于所述次循环的位数。构成：映射回路2内的位数被设定为与次循环1内的位数相同的三倍。因此，循环2的地址A2和A3被设置在与循环1上的地址A1相同的位置即使地址A2和A3位于环路2上的地址A1的位置。换句话说，环路1的A1与环路2的场F1-F3中的每一个重叠。因此，环路1的A1是基于循环2的地址A1，A2或A3，与循环1的A1同步地识别。因此，可以对磁性气泡存储元件进行控制。还可以将循环2内的位数设置为循环2内的位数的整数倍的整数倍。

14. 发明专利

JPS58222481A Magnetic bubble memory 失效
标题翻译：磁性气泡记忆
公开(公告)号：JPS58222481A
公开(公告)日：1983-12-24
申请号：JP10382282
申请日：1982-06-18
申请人： Hitachi Ltd
发明人： SUGIE MAMORU , TOYOOKA TAKASHI , AOKI HIROKAZU
IPC分类号： G11C11/14 , G11C19/08
CPC分类号： G11C19/0875
摘要： PURPOSE: To attain the assignment so as to decrease the hardware, by adopting an integral number for the determination of adjacent logical address interval (m) of magnetic bubble memories, where the integral number is in the relation of mutually prime with a bit number (n) in a minor loop out of integral numbers satisfying a prescribed equation.
CONSTITUTION: An integral number (m) being in the relation of mutually prime with the bit number (n) of one minor loop is selected among the integral numbers satisfying the equation of i=(2
α +1).2
β +1 or i=(2
α +1).2
β , and the adjacent logical addresses are set in the interval of m-bit in the minor loop. Thus, the assignment of addresses where the logic of the ALU used for the compiling calculation from the logical address into the physical address is simplified and the hardware and the software required for the address control are decreased, is attained.
COPYRIGHT: (C)1983,JPO&Japio
摘要翻译：目的：为了获得分配以减少硬件，通过采用整数来确定磁性气泡存储器的相邻逻辑地址间隔（m），其中整数与位数的互相关的关系（ n）在满足规定方程的积分数的次循环中。构成：在满足i =（2 + +1）的等式的整数中选择与一个次循环的位数（n）相互关联的整数（m）.2 <β > +1或i =（2 + 1）.2β，并且相邻的逻辑地址被设置在次循环中的m位的间隔中。因此，将用于编译计算的ALU的逻辑从逻辑地址分配到物理地址的地址的分配被简化，并且减少了地址控制所需的硬件和软件。

15. 发明专利

JPS5856186B2 JPS5856186B2 - 失效
公开(公告)号：JPS5856186B2
公开(公告)日：1983-12-13
申请号：JP12932980
申请日：1980-09-19
申请人： Hitachi Ltd
发明人： TOYOOKA TAKASHI , SUGIE MAMORU , AOKI HIROKAZU , YOSHIZAWA SHIGERU
IPC分类号： G11C11/14 , G11C19/08
CPC分类号： G11C19/085

16. 发明专利

JPS58189894A Magnetic bubble memory 失效
标题翻译：磁性气泡记忆
公开(公告)号：JPS58189894A
公开(公告)日：1983-11-05
申请号：JP7120982
申请日：1982-04-30
申请人： Hitachi Ltd
发明人： SUGIE MAMORU , TOYOOKA TAKASHI , AOKI HIROKAZU , SUZUKI MAKOTO , SUGITA KEN
IPC分类号： G11C11/14 , G11C19/08
CPC分类号： G11C19/0875
摘要： PURPOSE:To decrease the access time and to improve the data transfer speed, by performing the bubble transfer of a storage section, write section and a readout section independently and simultaneously. CONSTITUTION:A bubble of an address is divided and the last bubble reaches a detector after r1/f2. When the number of bits up to the address to be accessed next is r1.f1/f2 or below, the bubble of the address is transferred to the replicate gate during the readout of the split bubble, and the access time is reduced. In the write, the bubble is swapped in a storage loop after r2/f2 from the generation of the first bubble similarly, and the number of bits up to the address to be written is r1.f1/f2 or below, then while the bubble is generated in response to the data pattern, the bubble to be swapped out is transferred to the position of a swap gate while the bubble is generated in response to the data pattern, allowing to reduce the access time.
摘要翻译：目的：通过独立同时执行存储部分，写入部分和读出部分的气泡传输，减少访问时间并提高数据传输速度。构成：地址的气泡被划分，最后一个气泡在r1 / f2之后到达检测器。当直到接下来要访问的地址的位数为r1.f1 / f2或以下时，在读出分离气泡期间，地址的气泡被传送到复制门，并且访问时间减少。在写入时，类似地从第一个气泡的产生开始在r2 / f2之后的存储循环中的气泡被交换，并且要写入的地址的位数为r1.f1 / f2或更低，那么当气泡响应于数据模式而产生，当响应于数据模式产生气泡时，要被换出的气泡被转移到交换门的位置，从而减少访问时间。

17. 发明专利

JPS5897189A MAGNETIC BUBBLE MEMORY ELEMENT HAVING AUXILIARY STORAGE LOOP 失效
公开(公告)号：JPS5897189A
公开(公告)日：1983-06-09
申请号：JP19452181
申请日：1981-12-04
申请人： HITACHI LTD
发明人： TOYOOKA TAKASHI , AOKI HIROKAZU , SUGIE MAMORU
IPC分类号： G11C11/14 , G11C19/08
摘要： PURPOSE:To reduce the effective access time, by connecting a replicator respectively, between a minor loop and an auxiliary loop and between the auxiliary loop and a readout line. CONSTITUTION:Minor loops 1-1, 1-2... are connected with auxiliary loops 7-1, 7-2... having a capacitance being separated into integer of that for the minor loops via a replicator 8, and the loops 7-1, 7-2... are connected to a readout line 2 via a replicator 3. Thus, in copying the content of the desired part of the loops 1-1, 1-2... on the loops 7-1, 7-2..., the effective access time can be reduced substantially even for a large capacity magnetic bubble memory device.

18. 发明专利

JP2001326574A PHASE SYNCHRONIZATION CIRCUIT AND CLOCK GENERATION CIRCUIT 失效
公开(公告)号：JP2001326574A
公开(公告)日：2001-11-22
申请号：JP2000148580
申请日：2000-05-16
申请人： HITACHI LTD
发明人： SHIBAHARA YOSHIYUKI , KOKUBO MASARU , AOKI HIROKAZU
IPC分类号： H03L7/093 , H03L7/099
摘要： PROBLEM TO BE SOLVED: To provide a phase synchronization circuit and a clock generation circuit capable of keeping stability even in the case of low precision like a resistance element constituting an IC circuit. SOLUTION: The phase synchronization circuit consists of a phase comparator 1, a bias current supplying circuit 2, a charge pump 3, a loop filter 4, a voltage/ current converter 5, a current control oscillator 6 and a frequency divider 7. The comparator 1 detects the phase difference between a reference signal fref and the output fosc of the divider 7 and drives the next-stage charge pump 3 as UP and DN signals. The charging/discharging current of the pump 3 is decided by the circuit 2. As voltage smoothed by the filter 4, the output of the pump 3 is inputted to the converter 5 to be converted to a current output and drives the oscillator 6. The stability of the device including resistance 17 and resistance 12 is secured by the circuit 2 and the converter 5.

19. 发明专利

JPH1174762A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1174762A
公开(公告)日：1999-03-16
申请号：JP23205297
申请日：1997-08-28
申请人： HITACHI LTD
发明人： MIZUNO HIROYUKI , AOKI HIROKAZU , ISHIBASHI KOICHIRO
IPC分类号： G06F1/08 , G06F1/10 , H03K3/0231 , H03K3/03 , H03L7/00 , H03L7/081 , H03L7/089 , H03L7/099 , H03L7/18
摘要： PROBLEM TO BE SOLVED: To provide an oscillation circuit to supply a clock with low skew and low jitter to a logic circuit like a microprocessor, etc., and a memory circuit and to further provide a high-speed semiconductor integrated circuit device by the oscillation circuit. SOLUTION: In the oscillation circuit consisting of at least two ring oscillation circuits OSC1, OSC2 to OSCn to which plural inverters 110 to 11 m, 120 to 12 m, 1n0 to 1 nm are connected with many stages like a ring and conductive wiring, output of at least one inverter in the ring oscillation circuits OSC1 to OSCn is connected with the conductive wiring and the plural ring oscillators OSC1 to OSCn are oscillated with the same frequency. The oscillation circuit obtained by an above described means is structured as a voltage controlled oscillation circuit and a PLL is constituted by using a phase frequency comparator, a charge pump circuit and a low-pass filter. In addition, the conductive wiring of the oscillation circuit of the PLL is used as a global clock and the clock in the semiconductor circuit device is distributed by connecting a clock distribution system to the global clock. Consequently, the clock with low skew and low jitter is supplied to the logic circuit like the microprocessor, etc., and the memory circuit and furthermore, the high speed semiconductor integrated circuit device is achieved by the clock.

20. 发明专利

JPH05251561A 失效
公开(公告)号：JPH05251561A
公开(公告)日：1993-09-28
申请号：JP4823992
申请日：1992-03-05
申请人： HITACHI LTD
发明人： UCHIYAMA KUNIO , AOKI HIROKAZU , KUDO IKUO , NARITA SUSUMU , ARAKAWA FUMIO
IPC分类号： H01L21/82 , H01L21/3205 , H01L23/52
摘要： PURPOSE:To optimize a chip area and a delay time and minimize the man-hours related to layout in a semiconductor integrated circuit using a multilayered metal wiring technology by which a regular-structure block and a random block are integrated on one chip. CONSTITUTION:The most significant metal wiring layer is used for a bus wiring 127 to 132 in the inner part of an operating block 151 which is a regular- structure block. An intermediate metal wiring layer is used for a control signal 111 to 118. A control block 150, which is a random block, consists of an n- column standard cell 100. The least significant and the most significant metal wiring layer are used for a parallel wiring to the standard cell column which is a wiring between the standard cells and between the standard cell and the regular-structure block. The intermediate wiring layer is used for the wiring of a vertical direction. Thereby, a chip area and a delay time may be minimized and furthermore the man-hours of layout may be minimized.

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