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11. 发明专利

JPH022527A SYMMETRIC ELECTROCHROMIC DISPLAY DEVICE 失效
公开(公告)号：JPH022527A
公开(公告)日：1990-01-08
申请号：JP14571788
申请日：1988-06-15
申请人： HITACHI LTD
发明人： KANEKO HIROKO , MIYAKE SEIJI
IPC分类号： G02F1/153 , G09F9/30
摘要： PURPOSE:To restrain the occurrence of bubbles and to enhance the reliability of action and durability by forming electrochromic films not only on a 1st electrode but on a 2nd electrode and bringing the facing electrochromic films into contact with each other through an electrolyte. CONSTITUTION:On a transparent conductive film 1, glass substrates 2 possessing the electrochromic films (WO films) 3a and 3b are bonded to a substrate-spacer- substrate through two spacer 5 to assemble them integrally, and the electrolyte 6 is poured into the spacers 5 and 5, thereby constituting the title device. Since the electrochromic film 3b is formed on the 2nd electrode in such a way, the transparent conductive film 1 does not directly come into contact with the electrolyte 6, whereby the action of electrons and protons in the electrolyte 6 can be prevented. Accordingly, only the electrochromic films, electrons and protons act in the electrochromic films 3a and 3b. As a result, the occurrence of bubbles can be suppressed to enhance the reliability of actions and durability.

12. 发明专利

JPH01243460A MANUFACTURE OF SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01243460A
公开(公告)日：1989-09-28
申请号：JP6944588
申请日：1988-03-25
申请人： HITACHI LTD
发明人： SAGAWA MASAKAZU , KANEKO HIROKO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To enable electrically positive connection by conducting silicidation extending from the surface of a source or a drain on the trench side of the source or the drain in a switching MISFET over the surface of the upper end of an electrode in the trench. CONSTITUTION:A trench 9 is cut to the main surface of a semiconductor substrate 1, electrodes 11, 13 are formed into the trench 9, a switching MISFET is shaped near the trench 9, and silicidation or selective CVD is performed extending over the surface of the upper end of the electrode 13 from the surface of a source or a drain on the trench side in the source or the drain (an n type semiconductor region 6). Consequently, since the source or the drain 6 and the electrode 13 are connected, a silicide film or a silicon film can be shaped onto the surface of the electrode 13 and the surface of the source or drain 6 in the switching MISFET even when an silicon oxide film slightly remains on these surfaces. Accordingly, the laminated electrode and the source or the drain can be connected electrically and positively.

13. 发明专利

JPS64756A SEMICONDUCTOR DEVICE AND CAPACITOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS64756A
公开(公告)日：1989-01-05
申请号：JP5347288
申请日：1988-03-09
申请人： HITACHI LTD
发明人： OJI YUZURU , KASAHARA OSAMU , TADAKI YOSHITAKA , KANEKO HIROKO , MINE TOSHIYUKI , YAGI KUNIHIRO
IPC分类号： H01L27/04 , F02B3/06 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/51 , H01L29/92
摘要： PURPOSE:To obtain a semiconductor device having a capacitor, wherein a highly reliable capacitor insulating film is formed on a polycrystalline silicon film, when a silicon nitride layer is formed on a silicon oxide layer, a part of the thickness of said silicon nitride layer is oxidized, and a silicon oxide layer is formed, by determining the thickness of the silicon nitride layer within a specified range. CONSTITUTION:A silicon nitride film 26 is formed on the surface of polycrystalline cilicon by chemical vapor growth method. Then, a silicon oxide layer 24 is formed on the surface of the polycrystalline silicon when said silicon nitride film 26 is formed. The silicon nitride film 26 is formed on the silicon oxide layer 24 without forming an oxide film any more. Thereafter, the surface of the silicon nitride film 6 is oxidized. At this time, the thickness of the silicon nitride film 26 becomes 18.6nm or less. When the surface of the silicon nitride film is oxidized, the thickness of the remaining silicon nitride film 26 is made to be 3nm or more. Thus the occurrence of local oxidation of a lower polycrystalline silicon electrode 20 is prevented. Therefore, very high reliability can be achieved when the multilayered insulating films are formed on the polycrystalline silicon and a capacitor is formed.

14. 发明专利

JPS61287227A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS61287227A
公开(公告)日：1986-12-17
申请号：JP12815785
申请日：1985-06-14
申请人： HITACHI LTD
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L29/78 , H01L21/28
摘要： PURPOSE:To increase the depth of a semiconductor region at the end of a field insulating film by removing a nonsilicified portion of a high melting point metal layer formed on a substrate, and then implanting an impurity. CONSTITUTION:A high melting point metal layer 8 is coated on the entire surface of a substrate 1 exposed when a field insulating film 2, a gate electrode 5, a side wall insulating film and a film 7 are formed. Then, the substrate 1 and the layer 8 on the electrode 5 are annealed to form a silicide layer 9. Then, the unreacted layer 8 is wet etched to implant an n-type impurity to the substrate 1, and annealed to form an n type semiconductor region 6A and an N type semiconductor region 6B. Then, an insulating film 10, a connecting hole 11 and a conductive layer 12 are sequentially formed. According to this method, to implant the impurity after the unreacted layer 8 is removed, an impurity is implanted deeply to the end of the film 2, and the depth of the bonding surface between the region 6B and a channel stopper region 3 is increased. Thus, the insulating withstand voltage between the layer 9 and the region 3 can be improved.

15. 发明专利

JPS61125046A Manufacture of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造
公开(公告)号：JPS61125046A
公开(公告)日：1986-06-12
申请号：JP24600284
申请日：1984-11-22
申请人： Hitachi Ltd
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L21/3205 , H01L23/52 , H01L21/88
摘要： PURPOSE:To oxidate a metal film on a field insulating film and to prevent an unnecessary silicide layer from forming on the field insulating film by forming a silicide layer in an atmosphere containing oxygen. CONSTITUTION:After semiconductor regions 6a and 6b are formed, a high melting point metal layer 10a, for instance, a titanium layer is formed all over a semiconductor substrate 1, and is annealed in a gas atmosphere such as neon, argon and nitride containing about 0.1-10% oxygen, a high melting point metal layer 10a and the semiconductor substrate 1 are reacted, and a conductive layer 10 of silicide is formed. A diffusion of silicon onto the field insulating film 2 is controlled through oxidating the high melting point metal layer 10a in an atmosphere containing the said oxygen. Therefore, unnecessary silicidation of the high melting point metal layer 10a on the field insulating film 2 and a side wall 12 is prevented.
摘要翻译：目的：通过在含氧气氛中形成硅化物层，在场绝缘膜上氧化金属膜，防止不必要的硅化物层形成在场绝缘膜上。构成：在形成半导体区域6a和6b之后，在整个半导体衬底1上形成例如钛层的高熔点金属层10a，并在诸如氖，氩和氮化物等气体气氛中退火，使0.1-10％的氧，高熔点金属层10a和半导体衬底1反应，形成硅化物的导电层10。通过在含有氧的气氛中氧化高熔点金属层10a来控制硅到场绝缘膜2上的扩散。因此，防止了场绝缘膜2和侧壁12上的高熔点金属层10a的不必要的硅化。

16. 发明专利

JPS60239052A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS60239052A
公开(公告)日：1985-11-27
申请号：JP9444184
申请日：1984-05-14
申请人： HITACHI LTD
发明人： KOYANAGI MITSUMASA , KANEKO HIROKO
IPC分类号： H01L29/78 , H01L21/8244 , H01L27/10 , H01L27/11
摘要： PURPOSE:To enable to improve the integration degree of an SRAM by a method wherein a high-resistance load element and an MISFET, which constitutes an FF, are buried in a fine hole provided in the semiconductor substrate in the SRAM having a memory cell constituted of the high-resistance load element and the MISFET. CONSTITUTION:An n type buried layer 4, whereon the reference voltage VSS is impressed, is provided in the surface layer part of an n type Si substrate 1, whereon the supply voltage VCC is impressed, and a p type layer 3 for MISFET formation is made to epitaxially grow on the whole surface including the layer 3. A fine groove 6, which intrudes in the substrate 1 while being made to penetrate the buried layer 4, is bored and an n type region 10, which is used for improving the contact of the groove 6 and the substrate 1, is provided under the base face of the groove 6. U-shaped insulating films 7 are formed on the sidewalls of the fine groove 6 and the film 7 on one side of the films 7 is made to extendedly provided on the layer 3 for using as a gate insulating film 12. Moreover, a conductive layer 8 is buried in each U- shape of the films 7 and a high-resistance load element 11 is buried in the hollow part between the films 7. After that, a gate electrode 15 is mounted on the film 12 being provided extendedly, a gate electrode 14 is provided stretching over both of the films 7, and an n type source region 17 and an n type drain region 17 are formed on the lower sides of the gate electrodes 14 and 15 through the films 7.

17. 发明专利

JPS60136376A SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPS60136376A
公开(公告)日：1985-07-19
申请号：JP24381083
申请日：1983-12-26
申请人： HITACHI LTD
发明人： KANEKO HIROKO , KOYANAGI MITSUMASA
IPC分类号： H01L21/336 , H01L29/78
摘要： PURPOSE:To prevent mutual conductance among elements from reduction and improve the performance characteristics thereof in an MISFET of an LDD structure by a method wherein source/drain regions are made of a first, second, third layers diffused with different density of impurities. CONSTITUTION:A field insulating film 4 and thin oxide film 5 are selectively formed on the surface of a substrate. A polycrystalline Si layer 6 to act as gate is given treatment to be ready to serve as a conductive layer and is subjected to etching for the oxidation of its surface. An N type impurity, typically P, is injected into the oxidized surface. Next, an SiO2 film is deposited to cover the entire surface. The SiO2 film is exposed to anistropic etching for the formation of a side wall 8, composed of retained SiO2 film, on the sides of the gate 6. In a following process for the formation of an N type impurity layer 2, the side wall 8 and gate electrode 6 serve as a mask for the introduction of an N type impurity into the Si substrate. The source/drain layers are constituted of three impurity-diffused layers, that is, an N type layer 2, N type layer 12, and an N type layer 3.

18. 发明专利

JPH03129761A MANUFACTURE OF SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03129761A
公开(公告)日：1991-06-03
申请号：JP26612989
申请日：1989-10-16
申请人： HITACHI LTD
发明人： KANEKO HIROKO
IPC分类号： H01L27/04 , H01L21/265 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To restrict formation of natural oxide film on a polycrystalline silicon layer and to enhance storage capacity of charge by forming an insulating film on the polycrystalline silicon layer and then implanting impurities into the polycrystalline layer through the insulating film. CONSTITUTION:The surface of a semiconductor substrate 1 is oxidized between field insulating films 2 to form a gate insulating film 4, an undoped polycrystalline silicon is then formed entirely on the semiconductor substrate 1 and subjected to phosphorus treatment. A silicon oxide film is then formed entirely on the polycrystalline silicon and subjected to selective etching thus forming a gate electrode. An n-type impurity section of phosphorus, for example, is then formed through ion implantation on the surface of the semiconductor substrate 1 which is then annealed to provide n -type source and drain regions. A silicon oxide film is then formed entirely on the semiconductor substrate 1 to form a side wall 7. An undoped polycrystalline silicon layer is then formed entirely on the surface of the semiconductor substrate 1 followed by formation of an insulating film such as a silicon oxide film.

19. 发明专利

JPS6480060A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6480060A
公开(公告)日：1989-03-24
申请号：JP23591187
申请日：1987-09-19
申请人： HITACHI LTD
发明人： KANEKO HIROKO , OZAWA MASAMI , HIRAIWA ATSUSHI
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
摘要： PURPOSE:To contrive accomplishment of both improvement in dielectric withstand voltage and reduction in number of defects of a dielectric film by a method wherein, in a stacked structure DRAM, the dielectric film of a capacitor element is formed with a silicon nitride film and the silicon oxide film formed on the surface of said nitride film by high pressure oxidization. CONSTITUTION:The first electrode layer 13 of the capacitor C, to be used for retension of information, is connected to one electrode 13A of an MOSFET Qs to be used for selection of a memory cell. A silicon nitride film 14A is deposited on the surface of the n-type polysilicon electrode layer 13 using a CVD method, and a part of the nitride film 14A is formed into an oxide film 14B using a high-pressure oxidizing method. The second electrode layer 15, consisting of n-type polysilicon, is laminated on the film 14B. As the nitride film 14A is adopted as a dielectric film 14, the defect on the film is few, and a leak current is reduced. As the oxide film 14B is formed on the film 14A, the leak current is reduced all the more.

20. 发明专利

JPS63293980A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS63293980A
公开(公告)日：1988-11-30
申请号：JP12825687
申请日：1987-05-27
申请人： HITACHI LTD
发明人： KANEKO HIROKO , SUGIURA JUN
IPC分类号： H01L23/522 , H01L21/336 , H01L21/768 , H01L29/78
摘要： PURPOSE:To simplify the structure of a gate electrode for a MISFET by connecting the gate electrode and a wiring as an upper layer in an active region in the MISFET and forming a barrier metallic layer between the gate electrode and the wiring in a semiconductor integrated circuit device with the MISFET. CONSTITUTION:A barrier metallic layer 10 is constituted between a gate electrode 5 and a wiring 12 connected in an active region. The barrier metallic layer 10 is composed of a conductive nitride shaped by nitrifying a titanium silicide film 5B in the gate electrode 5 in a region specified by a connecting hole 9A. The barrier metallic layer 10 prevents a diffusion to a semiconductor substrate 1 through the gate electrode 5 and a gate insulating film 4 of aluminum in the wiring 12, thus obviating the deterioration of device characteristics due to the short circuit of the semiconductor substrate 1 and the wiring 12. Accordingly, since the barrier metallic layer 10 is only organized onto the gate electrode 5, complicate constitution in which a substance blocking the diffusion of aluminum is buried into the gate electrode 5 is removed, thus simplifying the structure of the gate electrode 5.

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