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    • 11. 发明专利
    • NONCONTACT TYPE IC CARD
    • JPH1173481A
    • 1999-03-16
    • JP23209397
    • 1997-08-28
    • HITACHI LTD
    • TANIGAWA HIROYUKITAKEUCHI MIKI
    • G11C14/00G06K17/00G06K19/07G11C5/14G11C11/22G11C16/06G11C16/24H02J17/00
    • PROBLEM TO BE SOLVED: To obtain a memory for a noncontact type IC card which has a long communication distance and low power consumption, and performs excellent low-voltage operation by providing a voltage generating circuit which generates a 1st positive source potential from the positive potential component of an AC signal and a negative source potential from the negative potential component of the AC signal. SOLUTION: The AC signal sent with an electromagnetic wave such as a microwave is received by an LC tuning circuit 110 and demodulated by a modulating and demodulating circuit 130. Further, the received signal is inputted to a voltage generating circuit 120 as AC electric power. The voltage generating circuit 120 rectifies the AC electric power to generates a positive potential V1 and a negative potential V2 at the same time and supplies them as driving electric power to the modulating and demodulating circuit 130, a nonvolatile memory 140, and a microprocessor 150. In this constitution, the voltage generating circuit 120 generates the two positive and negative potentials from the inputted AC signal, so the communication distance (distance between a card-side coil and the coil of a device which reads and writes the card) can be increased.
    • 16. 发明专利
    • SEMICONDUCTOR NONVOLATILE MEMORY
    • JPH09134594A
    • 1997-05-20
    • JP28959695
    • 1995-11-08
    • HITACHI LTD
    • TANIGAWA HIROYUKITAKEUCHI MIKI
    • G11C14/00G11C11/22
    • PROBLEM TO BE SOLVED: To obtain a highly reliable, highly integrated nonvolatile ferroelectric memory exerting a long life to a fatigue of a ferroelectric capacitor, by constituting the memory of a memory cell for storing information and a dummy cell for judging stored information. SOLUTION: The drawing shows a constitution of a cell of a ferroelectric memory. A pair of data lines DLMm and BLMm wherein (m) is the order of an array are coupled to one sense amplifier per unit array. To each data line are connected (n) memory cells consisting of a ferroelectric capacitor CFE and a field effect transistor, and a dummy cell of a combination of a cell of the same shape as the memory cell and a cell of a paraelectric capacitor CO and a field effect transistor. The ferroelectric capacitor of the dummy cell is polarized in a direction not to cause a polarization inversion during the operation. A capacity of the paraelectric capacitor CO is determined to be lower than an intermediate value of potentials of two signals output to the data line corresponding to binary information stored in the memory cell.