专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明专利

JPH08278895A DATA PROCESSOR 失效
公开(公告)号：JPH08278895A
公开(公告)日：1996-10-22
申请号：JP35325695
申请日：1995-12-27
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G11C17/00 , G06F9/22 , G06F9/24 , G06F9/445 , G06F9/46 , G06F9/48 , G06F11/00 , G06F11/14 , G06F12/06 , G06F13/00 , G06F15/78 , G11C16/02 , G11C16/06
摘要： PURPOSE: To improve the safety of a system at the time of the on-board writing of a program memory. CONSTITUTION: The part of an incorporated RAM 13 is moved to a vector address area by a bus controller 27. Even when an interruption is generated during the deletion or writing of an incorporated ROM 18, a right vector address is obtained. As a result, the runaway of a microcomputer is prevented and the safety of a system at the time of the on-board writing of the incorporated ROM 18 is improved.

12. 发明专利

JPH0594697A ASSOCIATIVE MEMORY AND MICRO COMPUTER INCORPORATED WITH THE MEMORY 失效
公开(公告)号：JPH0594697A
公开(公告)日：1993-04-16
申请号：JP7038392
申请日：1992-02-20
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G06F9/46 , G06F15/78 , G11C15/00 , G11C15/04
摘要： PURPOSE:To cope with the variety of pattern in using a database and also to shorter response time by incorporating a micro computer with an associative memory provided with an associative control interface. CONSTITUTION:The associative control interface 12 is provided, the position and size of field contributing to an associative operation are capable of setting from outside, and the interface is provided in the associative memory 67. The field that is set via this associative control interface 12 functions as an associative part contribution to the associative operation, and other fields function as the memory part of associative information. Thus, since the field contributory to the associative operation is made variable, the variety of its use pattern is enhanced in the case of forming data base in the associative memory. Also, by arranging the associative memory 67 in an address space controlled by a CPU, the time required for the retrieval of task control information is shortened.

13. 发明专利

JPS6446818A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPS6446818A
公开(公告)日：1989-02-21
申请号：JP20450887
申请日：1987-08-18
申请人： HITACHI LTD
发明人： IWATA KATSUMI
IPC分类号： G06F1/04 , G06F1/00 , G06F15/78 , H01L21/822 , H01L27/04
摘要： PURPOSE:To evade such a case where a low power consumption state is undesirably released and a malfunction is caused by using a control means that defines the release conditions for the low power consumption state in case the signals of different logical levels are supplied to the two prescribed input terminals. CONSTITUTION:A control circuit 5 defines the release conditions for a low power consumption state in case a 1st external input terminal receiving the reset signal RESET and a 2nd external input terminal receiving the HALT/INT signal are set at different logical levels. As a result, both external input terminals are never changed to the different logical levels at one time by such disturbance as the surge due to the electrostatic induction even in case both input terminals are changed undesirably by said disturbance. Thus it is possible to surely prevent such a case where the low power consumption state is undesirably released by such disturbance that issues a command to a CPU 1 for restarting before a system clock CLK is stabilized.

14. 发明专利

JPS6145336A Data processor 失效
标题翻译：数据处理器
公开(公告)号：JPS6145336A
公开(公告)日：1986-03-05
申请号：JP16637584
申请日：1984-08-10
申请人： Hitachi Ltd
发明人： IWATA KATSUMI
IPC分类号： G06F11/22 , G06F9/30 , G06F15/78
摘要： PURPOSE: To facilitate an easy check of an external terminal for input of a test instruction given from outside by controlling the writing/reading of an instruction given to an instruction RAM according to the control signal given from a test mode setting register provided inside a data processor or from outside.
CONSTITUTION: An instruction for test of external terminals R
0 WR
i is supplied during the input of a test instruction, and a writing operation is carried out to a test mode register within a test control circuit TCC to set the test mode of those external terminals. Then a multiplexer MPX is switched to cut off the output of instructions to an instruction decoder ID from an ROM and terminals R
0 WR
i . In stead the instructions of one or several words which are held by instruction I- RAM is repetitively read out and supplied to the decoder ID and executed. Then the test is given to terminals R
0 WR
i which are used for input of test instructions.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过根据从数据中提供的测试模式设置寄存器给出的控制信号来控制对指令RAM的指令的写入/读取，从而便于外部端子的输入，以便输入外部测试指令。处理器或从外部。构成：在测试指令的输入期间提供外部端子R0-Ri的测试指令，并对测试控制电路TCC内的测试模式寄存器进行写入操作，以设置这些外部端子的测试模式。然后，切换多路复用器MPX以从ROM和终端R0-Ri切断指令输出到指令解码器ID。代替由指令I-RAM保持的一个或多个单词的指令被重复读出并提供给解码器ID并被执行。然后测试用于输入测试指令的终端R0-Ri。

15. 发明专利

JPS6011949A DATA PROCESSING SYSTEM 失效
公开(公告)号：JPS6011949A
公开(公告)日：1985-01-22
申请号：JP11830483
申请日：1983-07-01
申请人： HITACHI LTD
发明人： KAWAMURA MASAMI , IWATA KATSUMI , FUNATSU KENZOU
IPC分类号： G06F11/10 , G06F12/16
摘要： PURPOSE:To increase the resistance of a data processing system to a hit of power supply, the surge voltage, etc. by providing an RAM to store parity bits, and reding and checking the corresponding parity bit in a data reading mode. CONSTITUTION:When the data on a program, etc. is written to an incorporated RAM2, the parity bit corresponding to the data is produced by a parity bit producing circuit 6 on the basis of the data supplied to the RAM2. Then the parity bit is written to an RAM7 for parity bit. When the data is read out of the RAM2, the parity bit related to the data is also read out of the RAM7. At the same time, a parity bit is newly produced and compared with the parity bit which is read out of the RAM7. Then an interruption signal is outputted when the discordance is detected from said comparison. Then a data processing system is reset to its initial state.

16. 发明专利

JPS59218561A Microcomputer 失效
标题翻译：微机
公开(公告)号：JPS59218561A
公开(公告)日：1984-12-08
申请号：JP9237383
申请日：1983-05-27
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： OGAWA HIROMASA , KII YOSHIO , FUNATSU KENZOU , IWATA KATSUMI
IPC分类号： G06F9/48 , G06F9/46 , G06F15/78
摘要： PURPOSE: To raise the degree of freedom of a program design by deciding a priority order of an interruption by a software, so that the priority order of plural interruptions can be set and changed freely and easily by a user side.
CONSTITUTION: Interruption request signals I
1 WI
4 are inputted to holding circuits F
2 WF
4 , respectively, and held. An interruption priority control means PID is interposed between the holding circuits F
1 WF
4 and interruption inputs P
1 W P
4 . This interruption priority control means PID is constituted of a kind of decoder consisting of a logical gate array. This control means PID is constituted so that a combination of a corresponding relation of the holding circuits F
1 WF
4 and the interruption inputs P
1 WP
4 can be optionally changed.
COPYRIGHT: (C)1984,JPO&Japio
摘要翻译：目的：通过确定软件中断的优先顺序来提高程序设计的自由度，使用户可以自由设置多个中断的优先顺序。构成：中断请求信号I1-I4分别输入到保持电路F2-F4并保持。在保持电路F1-F4和中断输入P1-4 P4之间插入有中断优先控制装置PID。该中断优先级控制装置PID由由逻辑门阵列组成的解码器的种类构成。该控制装置PID构成为可以可选地改变保持电路F1-F4和中断输入P1-P4的对应关系的组合。

17. 发明专利

JPS5917720A Successively comparing a/d converter having test function 失效
标题翻译：具有测试功能的成功比较A / D转换器
公开(公告)号：JPS5917720A
公开(公告)日：1984-01-30
申请号：JP12577682
申请日：1982-07-21
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HARADA MITSUFUMI , BABA SHIROU , IWATA KATSUMI
IPC分类号： G01R31/00 , G01D5/249 , H03M1/38
CPC分类号： H03M1/38
摘要： PURPOSE:To reduce the number of constituting elements and prevent the increment of the chip size, by adding the test function where the output of a comparator is outputted to an external terminal and contents of a successively comparing register can be increased. CONSTITUTION:A switch circuit 9 is provided between the output of a comparator 31 and the input of a control circuit 13. In the test mode, a switch MISFET 11 is turned off and a switch MISFET10 is turned on in the switch circuit 9, and the output of the comparator 31 is taken into a testing means through a terminal P31. In the normal A/D converting operation, switches MISFETs 11 and 10 are turned on and off respectively, and the output of the comparator is supplied to the control circuit 13 as it is, and a digital signal corresponding to the analog signal supplied to a terminal P11 is set to a register 8.
摘要翻译：目的：为了减少构成要素的数量，防止芯片尺寸的增加，通过增加比较器的输出输出到外部端子的测试功能，可以增加连续比较寄存器的内容。构成：开关电路9设置在比较器31的输出端和控制电路13的输入端之间。在测试模式中，开关MISFET 11断开，开关电路9中开关MISFET10导通，比较器31的输出通过端子P31被带入测试装置。在正常的A / D转换操作中，开关MISFET 11和10分别导通和截止，比较器的输出原样被提供给控制电路13，并将与提供给模拟信号的模拟信号相对应的数字信号端子P11设定为寄存器8。

18. 发明专利

JPS5911025A Resistance circuit in semiconductor integrated circuit 失效
标题翻译：半导体集成电路中的电阻电路
公开(公告)号：JPS5911025A
公开(公告)日：1984-01-20
申请号：JP11979882
申请日：1982-07-12
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： HARADA MITSUFUMI , BABA SHIROU , IWATA KATSUMI
IPC分类号： H01L21/822 , H01L27/04 , H03M1/76
CPC分类号： H03M1/685 , H03M1/765
摘要： PURPOSE:To improve the accuracy of conversion of an A/D conversion circuit using a resistance circuit, by connecting a terminal for level setting at least one of plural nodes of the resistance circuit for splitting reference voltage. CONSTITUTION:A ladder resistance circuit for splitting reference voltage in a D/A conversion circuits of plural resistance strings 5a-5d formed on a semiconductor chip. The strings 5a-5d are connected with each other by lines 6a-6c, a stable reference voltage Vref is applied to one end and the other end is connected to ground. The strings 5a-5d are provided with plural nodes N1-N4. An external terminal 8 for level setting is led from the intermediate point of the ladder resistance circuit. Thus, the potential of the intermediate point of the resistance circuit is fixed forcedly to Vref/2 in applying the Vref/2 to the terminal 8. Then, the potential at other nodes is also drawn to a desired potential and the error is reduced as a whole.
摘要翻译：目的：为了提高使用电阻电路的A / D转换电路的转换精度，通过连接用于电平设置的端子用于分压参考电压的电阻电路的多个节点中的至少一个。构成：用于在半导体芯片上形成的多个电阻线5a-5d的D / A转换电路中分配参考电压的梯形电阻电路。线5a-5d通过线6a-6c彼此连接，一端施加稳定的基准电压Vref，另一端连接到地。弦线5a-5d设有多个节点N1-N4。用于电平设定的外部端子8从梯形电阻电路的中间点引出。因此，将Vref / 2施加到端子8时，电阻电路的中间点的电位被强制地固定为Vref / 2。然后，其他节点的电位也被绘制到期望的电位，并且误差减小为整个。

19. 发明专利

JP2002342303A DATA PROCESSOR 失效
公开(公告)号：JP2002342303A
公开(公告)日：2002-11-29
申请号：JP2001142497
申请日：2001-05-14
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： HORIUCHI MICHIHIRO , IWATA KATSUMI
IPC分类号： G06F13/28 , G06F13/12 , G06F13/24 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To reduce the number of data registers with respect to the number of input channels in a peripheral circuit. SOLUTION: The data processor has a data transfer control circuit (3), with which data transfer can be controlled on the basis of the control of a central processing unit, and a peripheral circuit (16), and the peripheral circuit selects an input terminal like an input channel, processes input data from the selected input termina, requests the transfer of the processing result and outputs identification information (CH2-CH0), with which the relevant selected input terminal can be identified. The data transfer control circuit has a transfer destination address register (DAR), with which a plurality of low-order bits can be varied on the basis of the identification information from the peripheral circuit. In the transfer control circuit for transferring data processed by the peripheral circuit, a plurality of low-order bits of a transfer destination can be controlled from the side of the relevant peripheral circuit. Thus, it is not necessary for the peripheral circuit to be provided with a data register for storing the processing result of input data for every input terminal corresponding to every input terminal.

20. 发明专利

JP2002342266A DATA PROCESSOR 失效
公开(公告)号：JP2002342266A
公开(公告)日：2002-11-29
申请号：JP2001142498
申请日：2001-05-14
申请人： HITACHI LTD , HITACHI HOKKAI SEMICONDUCTOR
发明人： HORIUCHI MICHIHIRO , IWATA KATSUMI
IPC分类号： G06F12/00 , G06F5/10 , G06F12/02 , G06F13/38 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To reduce increase in chip area, due to an FIFO buffer for an input and output circuit. SOLUTION: A data processor (1) is provide with a central processing unit (2), a memory (5) which can be accessed from the central processing unit, a plurality of input/output circuits (12, 13), and an FIFO control circuit (6) for making the memory operate as the FIFO buffer of the input/output circuits. The FIFO control circuit is provided with a control means for specifying a plurality of memory areas to be used as the FIFO buffer by an area designating means, and for holding address information for read access and write access for each specified memory area by an address pointer means, and for FIFO operating the prescribed memory area, by using the address pointer means, in response to the request from the input/output circuit. Thus, it is not necessary to provide an FIFO buffer exclusively for the input/output circuit by a buffer realized of an in-chip memory and the FIFO control circuit, and the chip area and the costs can be reduced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式