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11. 发明专利

JPH01273451A DUPLICATED CLOCK SYNCHRONIZING SYSTEM 失效
公开(公告)号：JPH01273451A
公开(公告)日：1989-11-01
申请号：JP10360488
申请日：1988-04-26
申请人： FUJITSU LTD
发明人： MARUYAMA AKIRA , SHIRAI HIROAKI , NARA KOICHI
IPC分类号： H04L7/033 , G06F1/04 , H04L7/02
摘要： PURPOSE:To synchronize an output clock of a duplicated clock generating circuit by adding a simple gate circuit as a control circuit for a counter. CONSTITUTION:Control circuits 4N, 4E making a count start point for a counter 1N in use and a counter 1E not in use coincident with each other are provided to a clock generating circuit where PLL oscillators 2N, 2E, counters 1N, 1E and decoders 3N, 3E are provided duplicatedly through the gate processing a control signal H of one counter 1N by using the longest period clock in not only a decode output of its own counter 1N but also a decoded output of the other counter 1E. Then the output clocks N, E of the two systems of clock generators are synchronized. Thus, in case of selection and changeover by using a control signal USE deciding which of duplicated clocks is to be used, no data error takes place.

12. 发明专利

JPS6197798A Alarm generation system 失效
标题翻译：报警发生系统
公开(公告)号：JPS6197798A
公开(公告)日：1986-05-16
申请号：JP21801984
申请日：1984-10-17
申请人： Fujitsu Ltd
发明人： RYU TADAMITSU , TAKAHARA TOSHIO , YAMASHITA HIDEJI , SHIRAI HIROAKI , GOTO SHUNJI
IPC分类号： G08B25/00

13. 发明专利

JPS60214133A Data converting circuit 失效
标题翻译：数据转换电路
公开(公告)号：JPS60214133A
公开(公告)日：1985-10-26
申请号：JP7040884
申请日：1984-04-09
申请人： Fujitsu Ltd
发明人： IYOTA TOSHIO , OGURA TAKAYUKI , HASHIMOTO KENICHI , SHIRAI HIROAKI
IPC分类号： H04J3/00 , H04J3/18
CPC分类号： H04J3/18
摘要： PURPOSE:To decrease the converting delay time by storing data of a specific channel of a multiplex serial form to the 1st memory, reading the data in a burst way and applying prescribed converting processing, storing it in the 2nd memory and reading it. CONSTITUTION:A counter CRT1 designates a write address to a memory MEM1, gives a write command to a selector SEL1, writes a specific channel CH on the MEM1 sequentially, confirms the final m-th specific CH data inputted to the MEM1, reads the 1st m-th specific CH data in a burst way and applies a prescribed converting processing by a read processing circuit PRO. A counter CTR2 designates an address to a memory MEM2, writes the specific CH data on the MEM2 finished for processing via a selector SEL2, starts reading at the transmission point of time of the 1st specific CH of the next frame and transmits the processed data via the selector SEL. Thus, the delay time required for two frames in conventional systems is decreased to that of one frame's share.
摘要翻译：目的：通过将多路复用串行格式的特定通道的数据存储到第一个存储器来减少转换延迟时间，以突发方式读取数据并应用规定的转换处理，将其存储在第二个存储器中并读取。构成：计数器CRT1向存储器MEM1指定写入地址，向选择器SEL1发出写入命令，依次向MEM1写入特定的通道CH，确认输入到MEM1的最后的第m个特定CH数据，读取第1个 m特定CH数据，并通过读处理电路PRO执行规定的转换处理。计数器CTR2表示存储器MEM2的地址，经由选择器SEL2将特定CH数据写入已经完成处理的MEM2，在下一帧的第1特定CH的发送时刻开始读取，并经由选择器SEL。因此，传统系统中两帧所需的延迟时间减少到一帧的份额。

14. 发明专利

JPS60197048A Information transmitting device 失效
标题翻译：信息传输设备
公开(公告)号：JPS60197048A
公开(公告)日：1985-10-05
申请号：JP3351184
申请日：1984-02-24
申请人： Fujitsu Ltd
发明人： SHIRAI HIROAKI , OGURA TAKAYUKI , IYOTA TOSHIO , HASHIMOTO KENICHI
IPC分类号： H04L29/04 , H04L13/00 , H04L29/08
CPC分类号： H04L13/00
摘要： PURPOSE:To improve a flexibility for packaging of an information transmitting device by sending out time division binary information constituted by a code converting means by selecting a transmission rate in accordance with a transmission distance of a request device when a transfer request is generated. CONSTITUTION:An oscillating part 1 outputs a basic frequency required for obtaining a time, to a timepiece part 2. The timepiece part 2 divides an input frequency and generates a time of necessary year, month, day, hour, minute and second. An information assembling part 7 converts a time obtained from the timepiece part 2 to a binary code which has changed a transmission rate by a short distance use device and a long distance use device for sending it out, and sends it alternately by a time division to an interface control part 8. When a sending-out request of time information is received from the short distance device, the control part 8 selects a code of a high transmission rate used for a short distance, in the time information received from the assembling part 7, and when a sending-out request of time information from the long distance device, a code of a low transmission rate used for a long distance is selected and sent out.
摘要翻译：目的：通过发送由代码转换装置构成的时分二进制信息来提高信息发送装置的包装的灵活性，通过在产生转移请求时根据请求装置的传输距离选择传输速率。构成：振荡部1向时钟部2输出获取时间所需的基本频率。钟表部2分割输入频率，生成必需的年，月，日，时，分，秒的时间。信息组合部7将从钟表部分2获得的时间转换为通过短距离使用装置改变传输速率的二进制代码和用于发送的长距离使用装置，并且通过时分交替地发送到接口控制部8.当从短距离装置接收到时间信息的发送请求时，控制部8在从组装部接收到的时间信息中选择用于短距离的高传输速率的码如图7所示，并且当从长距离设备发送时间信息请求时，选择并发送用于长距离的低传输速率的代码。

15. 发明专利

JPS60160420A INITIAL SETTING SYSTEM OF MEMORY 失效
公开(公告)号：JPS60160420A
公开(公告)日：1985-08-22
申请号：JP1563584
申请日：1984-01-31
申请人： FUJITSU LTD
发明人： HASHIMOTO KENICHI , OGURA TAKAYUKI , IYOTA TOSHIO , SHIRAI HIROAKI
IPC分类号： G06F1/24 , G06F1/00 , G11C11/401
摘要： PURPOSE:To ensure the initial setting by resetting unstable information of a memory to initial set information at all times when the memory is mounted to the device and also at application of power in the transmitter where the memory unit is taken out or put in while the power is kept applied. CONSTITUTION:The memory unit consists of a power supply voltage detecting circuit 1 and a self-running counter 2 or the like and when the unit is mounted to the transmitter, a power voltage is applied to the said voltage detecting circuit 1 from a terminal A and detected. The detection signal sets an FF12, starts a self-running counter 2, which controls a selection circuit 4 and an output of an ROM5 is transmitted to an RAM3. Moreover, the initial set information written in the RAM3 is stored in advance in the ROM5. The content of the ROM5 is read by an address commanded by an address counter 6 and wirtten in the RAM3 by the said address. When the write is finished, the self-running counter 2 is stopped to reset the FF12 and the selection circuit 4 transmits the data to be processed from a terminal B to the RAM3.

16. 发明专利

JPS60117109A INFLOW OF WATER TO LAKE CALCULATION SYSTEM 失效
公开(公告)号：JPS60117109A
公开(公告)日：1985-06-24
申请号：JP22604383
申请日：1983-11-30
申请人： FUJITSU LTD
发明人： IMAI KAZUYOSHI , SHIRAI HIROAKI , UEDA KATSUHIKO
IPC分类号： G01F1/00
摘要： PURPOSE:To calculate an inflow of water simply with a minimum error, by installing a water-level measurement point an each of n rivers flowing into a lake respectively, by calculating the inflow of each river according to each water- level and calculating the inflow to the lake from said rivers considering time lags. CONSTITUTION:Water-level measurement points H1-Hn are installed on each of a plurality of rivers S1-Sn flowing into a lake. In a river Sk, the inflow to the lake from said river Sk is calculated from river inflow Qrk at the measurement point Hk, and ratio of a basin area Ak1 of the river Sk to a basin area Ak2 on the upper reach of the point Hk. A total inflow for all the rivers is calculated adding a possible time-lag factor to the inflow for the measurement point. (Refer to Equation 1). As far as a river with a small basin area is concerned, a calculation is available by integrating this area into that of a river with a larger basin area.

17. 发明专利

JPH11215090A FAILURE EVALUATION SYSTEM 失效
公开(公告)号：JPH11215090A
公开(公告)日：1999-08-06
申请号：JP1047498
申请日：1998-01-22
申请人： FUJITSU LTD
发明人： TANAKA YOKI , SHIRAI HIROAKI , MIYAWAKI HIROTOMO
IPC分类号： H04L1/00 , H04J3/02 , H04J3/14 , H04L5/22 , H04L12/24 , H04L12/26
摘要： PROBLEM TO BE SOLVED: To provide with a simple configuration a failure evaluation system which evaluates a failed package in an intra-device package. SOLUTION: This failure evaluation system which has a distributed time switch configuration consists of a means, which evaluates a failure of every package, adds a supervisory bit to sending data, and sends it to a time division multiple bus 3, a supervisory bit checking means 4 which checks the state of a supervisory bit of received data, and an alarm supervising means 5 which receives an output of the supervisory bit checking means and evaluates a failure package according to the state of a supervisory bit of received data and the course direction of the time division multiple bus.

18. 发明专利

JPH0955746A PHASE JUMP PREVENTION SYSTEM FOR CBR SIGNAL 失效
公开(公告)号：JPH0955746A
公开(公告)日：1997-02-25
申请号：JP20583895
申请日：1995-08-11
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： UCHIDA KAZUHIRO , TAKAO SHINJI , SHIRAI HIROAKI , HASHIMOTO KENICHI , WATANABE TOSHIAKI , OTA SHINJI , UEMATSU HITOSHI
IPC分类号： H04J3/00 , H04L7/08 , H04L12/28 , H04L12/66 , H04L12/70 , H04L12/951 , H04Q3/00
摘要： PROBLEM TO BE SOLVED: To prevent a phase jump by switching only a pointer value to a last frame value when a discarded cell includes a pointer. SOLUTION: A pointer process means 5 extracts a pointer indicating the head position of the frame phase included in a read CBR signal according to a pointer value instructed by a cell pointer process means 4 and the read phase of the CBR signal from a buffer means 1 is controlled. At this time, a last pointer holding means 6 also inputs and holds the same pointer and further holds the last received pointer at the same time, thereby generating the pointer of the last frame from its output side. Then a switching means 7 selects and outputs the signal passed through the pointer process means 5 except the pointer value of the CBR signal to an SDH network, but when the output of an SN process means 2 displays cell discarding as to the signal at the instructed pointer position, switching is so performed as to select the last pointer. When the cell discarding is not generated, on the other hand, the pointer outputted from the pointer process means 5 is selected.

19. 发明专利

JPH08195986A FAULT ALARM DATA GATHERING DEVICE FOR COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH08195986A
公开(公告)日：1996-07-30
申请号：JP489595
申请日：1995-01-17
申请人： FUJITSU LTD
发明人： SATO HIROYUKI , HASHIMOTO KENICHI , MARUYAMA AKIRA , TSUJI HIDEO , SHIRAI HIROAKI
IPC分类号： H04Q9/00
摘要： PURPOSE: To shorten the time required for gathering fault alarm data relating the fault alarm data gathering device in the communication equipment on a large scale. CONSTITUTION: First, an entire data transmission means 1a transmits all the fault alarming data of a communication data processing part 1 to a fault alarm management part 2. Thereafter, a changed part data transmission means 1b transmits only the timewisely changed ones among the fault alarm data of the communication data processing part 1 to the fault alarm management part 2. In the fault alarm management part 2, based on the entire fault alarm data transmitted by the entire data transmission means 1a and the change part data transmitted by the changed part data transmission means 1b thereafter, a latest data reproducing means 2a reproduces the latest fault alarm data of the communication data processing part 1. As mentioned above, since the entire fault alarm data are transmitted only at first basically and only the changed part data are transmitted thereafter, when a changed part is less, a data amount transmitted from the communication data processing part 1 to the fault alarm management part 2 is substantially reduced and the time required for gathering the fault alarm data is shortened.

20. 发明专利

JPH06178340A SPATIAL SWITCHING DEVICE 失效
公开(公告)号：JPH06178340A
公开(公告)日：1994-06-24
申请号：JP32217992
申请日：1992-12-02
申请人： FUJITSU LTD
发明人： SHIRAI HIROAKI , KODACHI HIRONORI
IPC分类号： H04Q3/52
摘要： PURPOSE:To make the use of a small connector possible by reducing the number of wirings of a direction selection circuit, while recuring a direction selecting function, by dividing the parallel output of an interface, performing a direction selection and recoupling the output on the side of a selection output. CONSTITUTION:When a first channel of an input direction No.1 is switched to a output direction No.9, the direction No.1 and No.9 are connected and the direction selection of upper 4 bits is performed in a direction selection circuit 22 only for the time when it is allowable to the first channel. In the same way, the direction No.1 and No.9 are connected and the direction selection of low-order 4-bits is performed in a direction selection circuit 24 only for the time when it is allowable to the first channel. The output wirings of the upper 4-bits and the low-order 4-bits for the same direction of the circuits 22 and 24 are bundled and it becomes 8-bit parallel, and the signal of the first channel of the direction No.1 is switched to the direction No.9 and it is outputted.

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