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11. 发明专利

JPS57209569A MEMORY ACCESS DEVICE IN VECTOR PROCESSOR SYSTEM 失效
公开(公告)号：JPS57209569A
公开(公告)日：1982-12-22
申请号：JP9491081
申请日：1981-06-19
申请人： FUJITSU LTD
发明人： ITOU MIKIO , TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F15/78 , G06F17/16
摘要： PURPOSE:To obtain the mechanism for a data bus and a switching circuit with high speed and economical capabilities, by locating the switching circuit at the bidirectional bus memory side. CONSTITUTION:A bidirectional bus 31 is connected exclusively for an access pipeline unit 9(A) and a bidirectional bus 32 is provided exclusively for an access pipeline unit 1U(B). THe connection control for a switching circuit 33 is made with a pipeline control section 42 of a memory control unit 5. The control section 42 is provided with shift registers (A) and (B) storing control information corresponding to the access pipelines (A) and (B). The shift registers (A) and (B) are driven with a clock, the control information is outputted at the position of timing corresponding to the location of digit where the control information is stored and control signals required in the memory control unit as well as a connection instructing signal to a switching circuit 33 can be supplied via a decoder.

12. 发明专利

JPS57161955A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS57161955A
公开(公告)日：1982-10-05
申请号：JP4777281
申请日：1981-03-30
申请人： FUJITSU LTD
发明人： ITOU MIKIO , KASUYA NAOAKI , TAMURA HIROSHI , UCHIDA KEIICHIROU
IPC分类号： G06F12/00 , G06F12/06 , G06F17/16
摘要： PURPOSE:To access a large quantity of data in every cycle for the vector processing, by dividing bank numbers arranged in order of address by the number of memory units and assigning plural banks having the same remainder to the same unit. CONSTITUTION:In the computer system having a vector unit VU connected to a memory control unit, a main memory consists of plural memory units 1'-0-1'-3 having plural banks 2-0-2-15 respectively. Bank numbers arranged in order of address are divided by the number of memory units, and plural banks having the same remainder are assigned to the same memory unit, and each memory unit and a memory control unit 4' are connected by a pair of busses. Thus, a continuous large address region is accessed in every cycle in the vector processing.

13. 发明专利

JPS57113164A INFORMATION PROCESSOR 失效
公开(公告)号：JPS57113164A
公开(公告)日：1982-07-14
申请号：JP18804880
申请日：1980-12-31
申请人： FUJITSU LTD
发明人： TAMURA HIROSHI
IPC分类号： G06F12/06 , G06F12/00 , G06F13/16
摘要： PURPOSE:To reduce queuing by combining parallel access with block access. CONSTITUTION:The capacity of a data buffer BF is selected corresponding to the amount of data during block access. Access to a central processor CPU via a data buffer BF makes block access function in parallel. Therefore, the efficiency of bus utilization is improved to reduce queuing due to the memory in busy.

14. 发明专利

JPS57105077A MAIN STORAGE CONTROLLER 失效
公开(公告)号：JPS57105077A
公开(公告)日：1982-06-30
申请号：JP18122680
申请日：1980-12-23
申请人： FUJITSU LTD
发明人： ITOU MIKIO , NAKATANI SHIYOUJI , TAMURA HIROSHI , OINAGA YUUJI
IPC分类号： G06F12/00 , G06F12/06 , G06F13/18 , G06F17/16
摘要： PURPOSE:To change the time of delay and to prevent a processor from stay of the data, by providing a means which delays the start by a prescribed cycle between the priority to a main storage device and the start of the next priority in accordance with an indication given from a vector processor. CONSTITUTION:A main storage controller 3 is connected between a vector processor 1 and main storage devices 2-1-2-4, and the data of the devices 2-1-2-4 are loaded to the processor 1. The data processed by the processor 1 is stored in devices 2-0-2-4. A 4-bit interval index ID given from the processor 1 is applied to a port 31 of the device 3, and an access request RD is supplied to the port 31 via a buffer 32. The output of the port 31 is applied to a decrementer 33. An interval of n cycle (n=0.1-) is secured between the start of priorities P1-P4 given to devices 2-0-2-4 from the processor 1 and the start of the next priorities P2-P1. Thus the capacity is reduced for the buffer 32 to prevent the processor 1 from stay of the data.

15. 发明专利

JPS5789173A DATA PROCESSING CONTROL SYSTEM 失效
公开(公告)号：JPS5789173A
公开(公告)日：1982-06-03
申请号：JP16410080
申请日：1980-11-21
申请人： FUJITSU LTD
发明人： UCHIDA KEIICHIROU , TAMURA HIROSHI , OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F17/16 , G06F9/38
摘要： PURPOSE:To process data, by placing consecutive elements of a vector register in sequence of corresponding banks so that each bank corresponds to an element of the same rank at every vector register, and prescribing a time limit for accessing the element. CONSTITUTION:A shift register consisting of 8 bits is used for generating the timings A-H, so that start signals of addition processing, multiplication processing, load processing and store processing are outputted from between A and B, D and E, and G, H and A, respectively. Access of one input of an adder 3 is started by the timing A, access of the other input of the adder 3 is started by the timing B in the same way, and after that, in the same way, access start of an output of the adder 3, access start of one input pf a multiplier 4, access start of the other input of 4, access start of an output of 4, operand access start of a load processing device 1, and operand access start of a store processor 2 are executed by C, D, E, F, G and H, respectively.

16. 发明专利

JPS5788595A REFRESHING SYSTEM 失效
公开(公告)号：JPS5788595A
公开(公告)日：1982-06-02
申请号：JP16410180
申请日：1980-11-21
申请人： FUJITSU LTD
发明人： ITOU MIKIO , TAMURA HIROSHI
IPC分类号： G11C11/406
摘要： PURPOSE:To realize the highly effective refreshing, by setting the logical storage number with which the refreshing can be started at a time when only the refreshing is carried out with the inhibition applied to the normal access at a large unit value and then starting the refreshing. CONSTITUTION:A counter 10 receives an emergent execution EMG.REF.GO signal. When lower bits ''0'' and ''1'' are set at ''0.0'', an AND circuit 13 conducts as long as all of 6-10 bits of a time counter 11 are set at ''1'' with 6 bits of the counter 10 set at ''0'' respectively. Then the block refresh BLK.REF signal is delivered to a priority and working check circuit 1. For signals ''0'' and ''0'' of bits 0 and 1 of the counter 10 which are supplied to the circuit 13, the logical storage connected to the 1st and 2nd bits of the counter 10 execute at a time the refreshing in the form of a block. As a result, the refreshing speed is increased up to a 4-fold value. Thus the refresh executing time is reduced to ensure the better efficiency.

17. 发明专利

JPS5757353A Memory access control system 失效
标题翻译：存储器访问控制系统
公开(公告)号：JPS5757353A
公开(公告)日：1982-04-06
申请号：JP13197080
申请日：1980-09-22
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI
IPC分类号： G06F12/14 , G01P21/00 , G06F12/00 , G06F12/06 , G06F12/10 , G06F17/16
CPC分类号： G06F12/10
摘要： PURPOSE:To realize a parallel process of both the conversion of address and the control of conflict and to increase the speed of access, by selecting a memory bank through the bit part of an address which requires no change when a logic address is converted into a physical address. CONSTITUTION:A processor that gives an access to a memory send first the part including (b) and (c) of bit Nos. 22-28 which are necessary for decision of the memory bank to a memory access controller 7 when an access request is given for a memory. At the same time, a logic address is converted into a physical address through an address conversion control bat 5. This conversion of address given no effect at all to the selection of memory bank and is accordingly is carried out independently of the conflict control of the access.
摘要翻译：目的：为了实现地址转换和冲突控制的并行处理，并提高访问速度，通过在逻辑地址转换成一个地址时不需要改变的地址的位部分选择一个存储器组实际地址。构成：一个访问存储器的处理器首先发送包括第22-28页的（b）和（c）部分的部分，这些部分是当访问请求是存储器访问控制器7时对存储器组决定存储器存取控制器7所必需的给予记忆同时，通过地址转换控制棒5将逻辑地址转换成物理地址。这种对地址的转换完全不影响到存储体的选择，并且因此独立于对访问。

18. 发明专利

JPS5733494A Key control system of main storage 失效
标题翻译：主要储存关键控制系统
公开(公告)号：JPS5733494A
公开(公告)日：1982-02-23
申请号：JP10588080
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： KOGA SATOSHI , UCHIDA KEIICHIROU , TAMURA HIROSHI , ITOU MIKIO , KASUYA NAOAKI
IPC分类号： G06F12/10 , G06F12/12 , G06F12/14 , G06F21/02
CPC分类号： G06F12/1466
摘要： PURPOSE:To increase the working speed of a memory system, by comparing the request newly accepted, if it is for writing, with the history held in each register and thus avoiding the repetition of exactly the same writing action. CONSTITUTION:An accepted request, if it is followed by the reading of a key memory, is stored after confirming that an unprocessed flag M of registers 1-1-1-n shown by a storage pointer 4 is off. In case the accepted request is only for writing, the request is compared with the contents of each register through comparators 2-1-2-n. And if a coincidence is obtained for the type, address and writing data respectively, the request is ignored regardless of the M flag. Otherwise the request is stored after confirming that the M flag indicated by the pointer 4 is off. If the M flag is on, the request of the corresponding register is processed to be retained until the M flag is turned off.
摘要翻译：目的：为了提高存储系统的工作速度，通过比较新接受的请求（如果是写入）与每个寄存器中保存的历史，从而避免重复完全相同的写入动作。构成：在确认存储指针4所示的寄存器1-1-1-n的未处理标志M被关闭之后，存储接受请求（如果紧随其后读取密钥存储器）。如果接受的请求仅用于写入，则通过比较器2-1-2-n将请求与每个寄存器的内容进行比较。并且如果分别获得类型，地址和写入数据的一致性，则无论M标志如何，忽略该请求。否则在确认指针4指示的M标志关闭之后存储请求。如果M标志为ON，则对相应寄存器的请求进行处理以保持M标志关闭。

19. 发明专利

JPS5730078A Vector data processor 失效
标题翻译：矢量数据处理器
公开(公告)号：JPS5730078A
公开(公告)日：1982-02-18
申请号：JP10554980
申请日：1980-07-31
申请人： Fujitsu Ltd
发明人： TAMURA HIROSHI , UCHIDA KEIICHIROU , OKAMOTO TETSUO , MIYANAGA HIDEO
IPC分类号： G06F17/16 , G06F15/78
CPC分类号： G06F15/8053
摘要： PURPOSE:To make access of vector registers efficiontly, by assigning the elements of the same number of each vector register to the same bank unit. CONSTITUTION:When vector data of vector registers VR0,VR1 are added and write-in instruction to a vector register VRn is executed, first elements #0-#m are sequentially read out from the register VR0 and applied to a register 4. The elements are read out from the vector register VR1 after one clock and applied to a register 5. The synchronism is taken for the read out vector data at a buffer register 6 and the element #1 of the register VR0 and the element #1 of the register VR1 are inputted to an operator 11 at the same time.
摘要翻译：目的：为了有效地访问向量寄存器，通过将相同数量的向量寄存器的元素分配给同一个单元。构成：当向量寄存器VR0，VR1的矢量数据被加上并且向量寄存器VRn的写入指令被执行时，从寄存器VR0顺序地读出第一个元件＃0-＃m并施加到寄存器4.元件在一个时钟之后从矢量寄存器VR1中读出并施加到寄存器5.在缓冲寄存器6和寄存器VR0的元件＃1和寄存器的元件＃1中对于读出向量数据进行同步 VR1同时输入到操作者11。

20. 发明专利

JPS5727364A Vector arithmetic control system 失效
标题翻译：矢量算术控制系统
公开(公告)号：JPS5727364A
公开(公告)日：1982-02-13
申请号：JP10205080
申请日：1980-07-25
申请人： Fujitsu Ltd
发明人： NAKATANI SHIYOUJI , UCHIDA KEIICHIROU , TAMURA HIROSHI
IPC分类号： G06F17/16 , G06F15/78 , G06F15/347
CPC分类号： G06F15/8053
摘要： PURPOSE:To generate a specific mask pattern with extreme easW by a specific value detecting means for mask operand specifying and a specific mask pattern generating means. CONSTITUTION:A specific value detecting means 10 of detecting a specific value for mask operand specifying, and a specific mask data generating means 11 of generating a prescribed specific mask pattern on the basis of the specific value are provided. When the specifying of a mask operand is detected by the means 10 during the execution of instructions, the means 11 generate the specific mask pattern, which is used as mask information.
摘要翻译：目的：通过用于掩模操作数指定的特定值检测装置和特定掩模图案生成装置来产生具有极小的特定掩模图案。构成：提供检测掩模操作数指定的特定值的特定值检测装置10以及基于特定值产生规定的特定掩模图案的特定掩码数据生成装置11。当在指令执行期间由装置10检测到掩模操作数的指定时，装置11产生用作掩码信息的特定掩模图案。

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