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11. 发明专利

JPS59220844A INSTRUCTION REEXECUTION CONTROL SYSTEM 失效
公开(公告)号：JPS59220844A
公开(公告)日：1984-12-12
申请号：JP9375383
申请日：1983-05-27
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI
IPC分类号： G06F11/14
摘要： PURPOSE:To retry an instruction where malfunction occurs and improve reliability by holding a vector instruction which is not executed even when a scalar instruction and a vector instruction are processed in parallel for the high speed execution of the instructions. CONSTITUTION:Scalar instructions and vector instructions are set up previously in a main storage device together. An instruction reexecution pointer register 26 controls the address of an instruction to be retried even if malfunction occurs to the instruction processed by a pipeline while the scalar instructions and vector instruction coexit and are processed sequentially. Namely, while the scalar instructions and vector instructions are processed in parallel for high-speed processing, a readout address register 35 points unexecuted instructions in an instruction word stack 29 unless the operands of both instructions do not coincide with each other. Consequently, the instructions pointed by the circuit 35 are read out of the circuit 29 even in case of malfunction and supplied through a selecting circuit 30 to a vector instruction decoding part 31 to be reexecuted.

12. 发明专利

JPS59771A Selection control system of operation processing section in data processor 失效
标题翻译：数据处理器的操作处理部分的选择控制系统
公开(公告)号：JPS59771A
公开(公告)日：1984-01-05
申请号：JP11103082
申请日：1982-06-28
申请人： Fujitsu Ltd
发明人： OKUYA SHIGEAKI
IPC分类号： G06F9/38 , G06F15/16 , G06F15/177 , G06F17/16
CPC分类号： G06F17/16
摘要： PURPOSE:To improve the processing efficiency, by adopting a selecting control system selecting taking the succeeding instructions into consideration for operating units in use by functions, in the execution of a common instruction. CONSTITUTION:When an instruction is an addition instruction using an addition unit or a multiplication unit, a certain instruction at an instruction outgoing waiting register 22 is decoded via an instruction extracting register 21, and in case of the addition instruction, the addition unit is started and the instruction information is shifted to a register 231 in an instruction managing section 23 in corresponding instructions to the addition unit. In giving the common instruction, if there is no room to select any operating unit, the unit possible for use is started. In the execution of the common instruction, if plural operating units are usable, the succeeding instructions are taken into account, the operating unit used by the succeeding instruction is discriminated and the common instruction is transmitted to other operating units with a selecting control section 26 of an instruction transmission control section 25.
摘要翻译：目的：为了提高处理效率，通过采用选择控制系统，选择将功能中使用的操作单元考虑在后的指令中，以执行公共指令。构成：当指令是使用加法单元或乘法单元的加法指令时，通过指令提取寄存器21对指令输出等待寄存器22的某个指令进行解码，在加法指令的情况下，加法单元开始并且指令信息在对加法单元的相应指令中被转移到指令管理部分23中的寄存器231。在给出通用指令时，如果没有选择任何操作单元的空间，则可以使用可能的单元。在执行公共指令时，如果多个操作单元可用，则考虑到后续指令，由后续指令使用的操作单元被识别，并且公共指令通过选择控制部分26发送到其他操作单元指令发送控制部25。

13. 发明专利

JPS57161938A INSTRUCTION CONTROL SYSTEM 失效
公开(公告)号：JPS57161938A
公开(公告)日：1982-10-05
申请号：JP4777481
申请日：1981-03-30
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , OKAGATA TETSUO
IPC分类号： G06F9/38 , G06F17/16
摘要： PURPOSE:To shorten the processing time considerably, by previding a register for holding information of an operation exeucting instruction, waiting registers for holding instruction before execution, and a means which compares the executing instruction with the instruction before exection to execute the instructions in order. CONSTITUTION:Instruction information is set to a fetch register 10. On condition that register interference check circuits 13-1 and 13-2 indicate non-register interference, a waiting register making control circuit 11 transfers instruction information of the fetch register 10 to a waiting register 12-1 or 12-2. A selector 14 selects the waiting register 12-1 or 12-2 by the control of a selecting control circuit 19. On condition that refister interference check circuits 18-1 and 18-2 indicate non-redister interference, an instruction transmission control circuit 15 transfers the output of the selector 14 to an adding register 17 or a multiplying register 16 and transmits start information for an operation processing part simultaneously.

14. 发明专利

JPS57155666A INSTRUCTION CONTROLLING SYSTEM OF VECTOR PROCESSOR 失效
公开(公告)号：JPS57155666A
公开(公告)日：1982-09-25
申请号：JP3953681
申请日：1981-03-20
申请人： FUJITSU LTD
发明人： SAKAMOTO KAZUSHI , OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F9/30 , G06F9/38 , G06F15/78 , G06F17/16
摘要： PURPOSE:To realize a vector processor with high performance, by attaining an effective application of a processing part for a vector processor containing plural processing parts. CONSTITUTION:When an instruction fetched from a main storage device 4 by an instruction fetching part 1 is identical with a vector instruction, this instruction is transferred to a vector processor. An instruction decoder 2 decodes the transferred vector instruction and gives the decoded result to an instruction controller 3 to control a load processing part 6, a store processing part 7, an operator 8 and a vector register memory 9 respectively. Thus the execution of an instruction is controlled. In such way, plural processing parts are used effectively.

15. 发明专利

JPS5710873A INSTRUCTION CONTROL DEVICE 失效
公开(公告)号：JPS5710873A
公开(公告)日：1982-01-20
申请号：JP8611180
申请日：1980-06-25
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , OKAMOTO TETSUO
IPC分类号： G06F9/38 , G06F15/78 , G06F17/16 , G06F15/347
摘要： PURPOSE:To execute a data processing efficiently, by constituting a device so that an operation control executing instruction is held by an operation control executing instruction holding means which has divided an operation control execution stage into plural parts, in accordance with a control signal from an operation processing means being of a pipeline structure. CONSTITUTION:In a data processing equipment for processing a vector instruction, an operation control execution stage in an instruction control device is divided into two by providing a setting circuit 7 for an ER stage, a register 8, a setting circuit 9 for an EW stage, a register 10, and decoders 11, 12. In accordance with a control signal from an operation processing part 14 being of a pipeline structure, an operation control executing instruction to each register 8, 10 is held. According to this constitution, since control of a write stage is started by an instruction from the operation processing part 14, the operation control is executed at a higher speed, and also an optimum data processing according to an actual control processing state is executed.

16. 发明专利

JPH0519736B2 失效
公开(公告)号：JPH0519736B2
公开(公告)日：1993-03-17
申请号：JP23757083
申请日：1983-12-16
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI
IPC分类号： G06F7/32 , G06F7/24 , G06F17/16

17. 发明专利

JPH0540777A BUTTERFLY OPERATION SYSTEM 失效
公开(公告)号：JPH0540777A
公开(公告)日：1993-02-19
申请号：JP19662991
申请日：1991-08-06
申请人： FUJITSU LTD
发明人： OKUYA SHIGEAKI , NAKAZURU TOSHIRO , KUBO SHINICHI
IPC分类号： G06F17/14 , G06F17/16
摘要： PURPOSE:To reduce the amount of hardware and to shorten the processing time by omitting normalization after multiplication in the butterfly operation in the fast Fourier transform processing. CONSTITUTION:Multilication results Ra Rb, Ia Ib, Ra Ib, and Ia Rb are stored in shift registers 14, 15, 16, and 17 respectively, and alignment is performed, and respective exponents of the real part and the imaginary part of a first operand A are equalized to Ea, and those of a second operand B are equalized to Ea. Subtraction and addition are performed by a subtractor 13 and an adder 19 to obtain FRy and Fly. Normalization is not performed, and Ea and Eb from comparators 12 and 13 are directly stored in an intermediate result operand register 40 as respective exponents of the real part and the imaginary part of an intermediate result operand Y, and operation results of the subtractor 13 and the adder 19 are stored in the intermediate result operand register 40 as respective exponents of the real part and the imaginary part.

18. 发明专利

JPH04114255A TRANSFER SPEED SWITCHING SYSTEM 失效
公开(公告)号：JPH04114255A
公开(公告)日：1992-04-15
申请号：JP23477390
申请日：1990-09-05
申请人： FUJITSU LTD
发明人： SEKINE MAKOTO , OKUYA SHIGEAKI , MASUDA JITSUO
IPC分类号： G06F13/38
摘要： PURPOSE:To use one interface both as a high-speed interface and as a low-speed interface by including information instructing own data transfer speed in a processing request command by the main processor of a processing request source. CONSTITUTION:Corresponding to the data transfer speed of the interface of a main processor 1, the code of the processing request is distinguished, and the data transfer speed of the interface of a slave processor 2 can be switched. Then, the slave processor 2 identifies the data transfer speed of the main processor at the processing request source according to the code of the processing request command transmitted from the main processor and switches the data transfer speed of the interface. Namely, input and output interfaces 11 and 12 are provided to enable operations while switching the high and low data transfer speed. Thus, the interface and a transfer bus common for the respective transfer speed can be used, and the data can be transferred between plural main processors and slave processors efficiently without lowering the performance.

19. 发明专利

JPS6161138B2 失效
公开(公告)号：JPS6161138B2
公开(公告)日：1986-12-24
申请号：JP14475479
申请日：1979-11-08
申请人： FUJITSU LTD
发明人： SHIMIZU KAZUYUKI , OKUYA SHIGEAKI
IPC分类号： G06F7/38 , G06F7/00 , G06F7/499 , G06F7/52 , G06F9/30

20. 发明专利

JPS6116111B2 JPS6116111B2 - 失效
公开(公告)号：JPS6116111B2
公开(公告)日：1986-04-28
申请号：JP8610980
申请日：1980-06-25
申请人： Fujitsu Ltd
发明人： OKAMOTO TETSUO , OKUYA SHIGEAKI
IPC分类号： G06F9/30 , G06F9/38 , G06F17/16
CPC分类号： G06F9/30079 , G06F9/3869

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