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11. 发明专利

JPH0378192A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0378192A
公开(公告)日：1991-04-03
申请号：JP21432289
申请日：1989-08-21
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： G11C11/41
摘要： PURPOSE:To reduce power consumption in a mode where an internal clock is generated by outputting the internal clock only when a memory select signal changes from an inactive state to an active state. CONSTITUTION:A memory select signal set at the active state for constant time after an address value Nm changes is supplied to an internal clock generation circuit 3. When the memory select signal changes from the inactive state to the active state, the internal clock (phi) is outputted from the internal clock generation circuit 3, and is supplied to a memory circuit 2. At the memory circuit 2, a bit line is charged with the internal clock signal (phi), and after charge, the bit line is discharged selectively corresponding to a stored content, then, the stored content is read out. Meanwhile, since no internal clock (phi) is generated even when the memory select signal changes from the active state to the inactive state, no unrequired internal clock (phi) is generated. In such a way, the power consumption in the memory circuit can be reduced.

12. 发明专利

JPH02194649A MASTER-SLICE-TYPE INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH02194649A
公开(公告)日：1990-08-01
申请号：JP1474089
申请日：1989-01-24
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , ABE KOJI
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H01L27/118
摘要： PURPOSE:To enable by-pass interconnections to be provided if required in a large-scaled macrocell and to improve degree of freedom in layout of interconnections by enlarging distances between basic cells arranged on a substrate to predetermined extents. CONSTITUTION:Basic cells 10 are arranged in matrix on a substrate for constituting a large-scaled macrocell such as a RAM, ROM or multiplier while they are spaced from each other by enlarged distances L1 and L2 which are at least as large as a width of one interconnection. First-layer metallic interconnections 11, 13, 15 are provided in the space L1 and second-layer metallic interconnections 12, 14, 16 are provided in the space L2 according to the aspect principle and the interconnections 11-16 are connected by contacts 17-20 to provide by-pass interconnections A and B. According to such arrangement, the by-pass interconnections can be provided as required within the large-scaled macrocell and the layout of interconnections can be designed with a higher degree of freedom.

13. 发明专利

JPH01294296A STATIC RANDOM ACCESS MEMORY 失效
公开(公告)号：JPH01294296A
公开(公告)日：1989-11-28
申请号：JP12411688
申请日：1988-05-20
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , ASAI KAZUYUKI
IPC分类号： G11C14/00 , G11C11/40 , H01L27/10
摘要： PURPOSE:To arbitrarily write an initial value at the time of forming a static random access memory (RAM) by providing a memory cell of the RAM with a read-only memory cell where the storage information initial value of the memory cell can be preliminarily stored. CONSTITUTION:An initial value write line 10 or 11 which connects a VDD power source wiring 12 or a VSS power source wiring 13 to the connection end of an inverter 2 or 3 through an N channel transfer gate (ROM cell) 9 is wired in a memory cell 1 of a conventional RAM, and a reset line 14 is wired in the gate of the ROM cell 9. When an arbitrary storage information initial value is written in the ROM cell 9 provided in the memory cell of this RAM at the time of forming the RAM, the steady state of the memory cell of the RAM is settled. Thus, though the initial value is permanently held without being changed because the ROM is non-volatile, contents of the memory cell of the RAM can be rewritten on demand thereafter.

14. 发明专利

JPH01294295A PARTIAL RANDOM ACCESS MEMORY 失效
公开(公告)号：JPH01294295A
公开(公告)日：1989-11-28
申请号：JP12411388
申请日：1988-05-20
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , SHIKATANI JUNICHI
IPC分类号： G11C8/14 , G11C8/16 , G11C11/41
摘要： PURPOSE:To arbitrarily partially access an arbitrary bit by constituting a memory cell array where plural partial access memory cells connected to plural word lines which can be activated independently of one another exist together. CONSTITUTION:When a first word line WL1 is selected at the time of accessing a first memory cell array 200, each memory cell MC1 can be accessed; and when a second word line WL2 is selected at the time of accessing a second memory cell array 300, each memory cell MC2 can be accessed. Since memory cell arrays different from one another are connected to plural word lines which can be activated independently of one another, write to only memory cells corresponding to the selected word line is possible, and thus, partial access is possible.

15. 发明专利

JPS63306640A PROGRAMMABLE LOGIC ARRAY 失效
公开(公告)号：JPS63306640A
公开(公告)日：1988-12-14
申请号：JP14249987
申请日：1987-06-08
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： H01L21/82 , H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/08 , H01L27/092 , H03K19/177
摘要： PURPOSE:To utilize basic cells efficiently by a method wherein the basic cell is composed of a CMOS forming part and an NMOS forming part and respective exclusive overlying lines of intersection are provided in an AND plane and an OR plane. CONSTITUTION:A programmable logic array PLA is formed by employing a master slice type semiconductor integrated circuit in which basic cells composed of CMOS forming parts 10a and NMOS forming parts 10b the constituted. A plurality of N-type channel MOS transistors composed of the basic cells 10 are provided at the cross points of input lines 36, 37, 40 and 41 and 1st overlying lines of intersection 38 and 39 in an AND plane. A plurality of N-type channel MOS transistors composed of the basic cells 10 are provided at the cross points of 2nd overlying lines of intersection 43 and 44 connected to the 1st overlying lines of intersection 38 and 39 and output lines 42 and 45 in an OR plane. With this constitution, the unused portions of the basic cells 10 are very little and the basic cells 10 can be utilized efficiently.

16. 发明专利

JP2003044536A Layout method and apparatus for lsi arranging cell with timing priority 有权
标题翻译：用于具有时序优先权的LSI安排单元的布局方法和装置
公开(公告)号：JP2003044536A
公开(公告)日：2003-02-14
申请号：JP2001228373
申请日：2001-07-27
申请人： Fujitsu Ltd , 富士通株式会社
发明人： NAGASAKA MITSUAKI , MIURA DAISUKE , OKAMOTO MASAYUKI , HONDA HIROYUKI , ARAKAWA TOSHIO , YOSHIDA SHUJI , YOSHIDA KENJI , KOBAYASHI KENJI
IPC分类号： G06F17/50 , H01L21/82
CPC分类号： G06F17/5068
摘要： PROBLEM TO BE SOLVED: To provide a layout method and apparatus as much capable as possible of wiring automatically after a cell arrangement with timing priority.
SOLUTION: In a layout method for LSI with a plurality of cells, cells are arranged automatically based on the net list including data on cells and their connections and on the timing conditions, and global wiring processing is performed to analyze a degree of complexity of wiring after an optimizing processing for timing to arrange a plurality of cells in a chip then within a small area in which determined it is hard to perform detailed wiring processing because of a high degree of complexity of wiring, and the detailed wiring processing is performed to the rearranged cells. Since the re-arrangement processing of cells is performed only in the small areas, it is possible to reduce in the degree of complexity while keeping the optimized status of timing of cells, so that it is reduced in possibility to cause a wiring impossibility due to the detailed wiring processing in the future.
COPYRIGHT: (C)2003,JPO
摘要翻译：要解决的问题：提供一种在具有定时优先级的单元布置之后尽可能多地布线的布局方法和装置。解决方案：在具有多个单元的LSI的布局方法中，基于包括关于单元及其连接的数据的网表自动布置单元，并且在定时条件下，执行全局布线处理以分析布线的复杂程度在对芯片中的多个单元进行优化处理之后，在由于布线复杂度高而难以进行详细布线处理的小区域内进行详细布线处理，重排细胞。由于仅在小区域中进行单元的重新配置处理，所以可以在保持单元的定时优化状态的同时降低复杂度，从而可能导致由于未来的详细布线处理。

17. 发明专利

JPH0371490A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0371490A
公开(公告)日：1991-03-27
申请号：JP20845589
申请日：1989-08-11
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： G11C11/41
摘要： PURPOSE:To perform data processing efficiently and speedily by providing a bit selecting means which selects some of bits of an address selected by an address selecting means and a 2nd data input/output means which inputs and outputs data for the selected bits. CONSTITUTION:A memory cell array 1 is so constituted that plural bits are assigned to one address, an address selecting means 2 can select addresses specified in a memory cell array 1 with address signals Ao - Am, and a 1st data input/output means 3 inputs and outputs data Do - Dn for the address. Further, a bit selecting means 4 selects some bits specified with bit select signals Co - Ch in the address selected by the address selecting means 2 and the 2nd data input/output means 5 inputs and outputs the data Do - Dp for the bits. Consequently, data can be rewritten as to any bits and the data processing is made efficient and fast.

18. 发明专利

JPH0287393A SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0287393A
公开(公告)日：1990-03-28
申请号：JP23722588
申请日：1988-09-21
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , SHIKATANI JUNICHI
IPC分类号： G11C11/418 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/41 , H01L21/8242 , H01L27/10 , H01L27/108
摘要： PURPOSE:To attain high-speed access by dividing plural transistors connected to a word line into plural groups and connecting a subword line to be commonly connected for each group through an inverter to a main word line. CONSTITUTION:For plural transistors composed of transistors connected to a main word line 3, they are divided into plural groups 16-1 and 16-2, and subword lines 7-1 and 7-2 connected commonly for respective groups are connected through inverters 17-1 and 17-2 to the main word line 3. Consequently, a buffer 14 of the main word line 3 is sufficient to have an output capacity for driving only prescribed one group. The inverters 17-1 and 17-2 are sufficient to be small for driving only the total of the memory cells. Thus, the access time can be shortened.

19. 发明专利

JPH0214495A READ ONLY MEMORY 失效
公开(公告)号：JPH0214495A
公开(公告)日：1990-01-18
申请号：JP16360488
申请日：1988-06-30
申请人： FUJITSU LTD
发明人： MIURA DAISUKE , ASAI KAZUYUKI
IPC分类号： G11C17/18 , G11C16/04 , G11C17/00
摘要： PURPOSE:To attain high speed of readout by providing a memory cell comprising a transistor (TR) pair whose gate is connected to a word line and a bit line pair of 2 line one pair in common, giving a ground potential to one bit line and giving a power potential to other bit line and detecting a difference voltage to the bit line pair. CONSTITUTION:Gates of 1st and 2nd TRs Q1, Q2 constituting each memory cell are connected in common to a word line WL, the bit line is constituted by it line pair of 2 line one pair, the source S of the 1st TR Q1 is connected to a ground potential VSS and the source S of the TR Q2 is connected to a power potential VDD. Then one bit line potential descends from an intermediate potential VMID to ground potential VSS and other bit line potential VMID rises from the intermediate potential to the power potential VDD, a potential difference is caused to the bit line pair and the potential difference is detected by a difference sense amplifier 5. Thus, the bit line potential is increased/decreased from the middle of the ground potential and the readout time is reduced.

20. 发明专利

JPH01238219A PROGRAMMABLE LOGIC ARRAY 失效
公开(公告)号：JPH01238219A
公开(公告)日：1989-09-22
申请号：JP6362388
申请日：1988-03-18
申请人： FUJITSU LTD
发明人： MIURA DAISUKE
IPC分类号： G06F7/00 , H03K19/177
摘要： PURPOSE:To rewrite the program of a programmable logic array by controlling information for connecting an addition transistor or not by information written in a static cell. CONSTITUTION:For instance, when a word line is externally selected in a RAM cell for storing '1', '0' information, transmission gates TR0, TR1 are turned on and prescribed information is written in inverter latches R0, R1 in the AND plane element of a PLA through a bit line BL, the inverse of BL. When the potential of the A point of the input side of the latches R0, R1 is '1', the output of the A point of an output side is defined to be '0' and accordingly, the connection of the addition transistor ANO and a product term line is separated. When the potential of the 3 point is '0..., they are connected. Accordingly, the prescribed information can be written to the PLA element.

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