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11. 发明专利

JP2008053914A Delay circuit, testing device, program, semiconductor chip, initialization method, and initialization circuit 有权
标题翻译：延迟电路，测试设备，程序，半导体芯片，初始化方法和初始化电路
公开(公告)号：JP2008053914A
公开(公告)日：2008-03-06
申请号：JP2006226478
申请日：2006-08-23
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： FUJITA KAZUHIRO , SUDA MASAKATSU , HASUMI TAKUYA
IPC分类号： G01R31/28 , H01L21/822 , H01L27/04 , H03K5/14
CPC分类号： G01R31/3016
摘要： PROBLEM TO BE SOLVED: To accurately measure the delay amount of a delay element. SOLUTION: The delay circuit comprises: a first delay element; a second delay element; and an initialization part for measuring the delay amount generated to each delay setting value by the first delay element and initializing the first delay element. The initialization part comprises: a first loop route for inputting the output signals of the first delay element to the first delay element; a second loop route for inputting the output signals of the second delay element to the second delay element; a first measurement part for successively setting a different delay setting value to the first delay element and successively measuring the delay amount of the first delay element; a second measurement part for measuring the delay amount in the second delay element in synchronism with the first measurement part without changing the delay setting value of the second delay element; and a delay amount calculation part for correcting the delay amount measured by the first measurement part by using the delay amount measured in synchronism with the delay amount by the second measurement part. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：准确测量延迟元件的延迟量。解决方案：延迟电路包括：第一延迟元件; 第二延迟元件; 以及初始化部，用于测量由第一延迟元件对每个延迟设定值产生的延迟量，并初始化第一延迟元件。初始化部分包括：第一循环路径，用于将第一延迟元件的输出信号输入到第一延迟元件; 第二循环路径，用于将第二延迟元件的输出信号输入到第二延迟元件; 第一测量部分，用于连续地对第一延迟元件设置不同的延迟设定值，并连续测量第一延迟元件的延迟量; 第二测量部分，用于在不改变第二延迟元件的延迟设定值的情况下与第一测量部分同步地测量第二延迟元件中的延迟量; 以及延迟量计算部，用于通过使用与第二测量部的延迟量同步测量的延迟量来校正由第一测量部测量的延迟量。版权所有（C）2008，JPO＆INPIT

12. 发明专利

JP2008029039A Delay device 有权
标题翻译：延迟装置
公开(公告)号：JP2008029039A
公开(公告)日：2008-02-07
申请号：JP2007267237
申请日：2007-10-12
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： OKAYASU TOSHIYUKI , SUDA MASAKATSU
IPC分类号： H03K5/14
摘要： PROBLEM TO BE SOLVED: To enhance delay time accuracy of a delay device by making fluctuation of supply voltage of the delay device small. SOLUTION: This delay device which delays input transmission signals is provided with a plurality of delay elements which are driven by two supply voltages V SS , V DD (V DD >V SS ), delay the input transmission signals, and are connected in series; and a plurality of addition circuits which output predetermined voltages larger than a supply voltage V SS and smaller than a supply voltage V DD to outputs of the plurality of delay elements, and which are connected to respective outputs of the delay elements, respectively. A delay element has a digital circuit which outputs either of binary output voltages in response to input voltages, and an addition circuit outputs a voltage almost in agreement with a threshold voltage which a digital circuit output reverses from one of the output binary voltages to the other. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：通过使延迟装置的电源电压波动较小来提高延迟装置的延迟时间精度。解决方案：延迟输入传输信号的延迟装置设置有多个延迟元件，它们被两个电源电压V SB SB，V SB SB（V < SB> DD > V SS ），延迟输入传输信号，并串联连接; 以及多个加法电路，其输出大于供给电压V SB SB的预定电压，并且小于供给电压V SB> DD 到多个延迟元件的输出，以及哪个分别连接到延迟元件的相应输出。延迟元件具有数字电路，其输出响应于输入电压的二进制输出电压，并且加法电路输出几乎与数字电路输出从输出二进制电压之一反转到另一个的阈值电压一致的电压。版权所有（C）2008，JPO＆INPIT

13. 发明专利

JP2007096520A Electronic device, load variation compensation circuit, power supply apparatus, and test apparatus 有权
标题翻译：电子设备，负载变动补偿电路，电源设备和测试装置
公开(公告)号：JP2007096520A
公开(公告)日：2007-04-12
申请号：JP2005280643
申请日：2005-09-27
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU
IPC分类号： H03K19/00 , H03K19/0948
CPC分类号： H03K19/00384
摘要： PROBLEM TO BE SOLVED: To provide a load variation compensation circuit for compensating power supply voltage variations due to fluctuation in a consumed current of an operating circuit. SOLUTION: The load variation compensation circuit is provided, which includes: a first delay circuit section whose delay amount is varied by a prescribed first variation amount per unit variation amount of a power supply voltage supplied to an operational circuit for delaying a clock signal which the first delay circuit section receives; a second delay circuit section prepared in parallel with the first delay circuit section and whose delay amount is varied by a prescribed second variation amount greater than the prescribed first variation amount per the unit variation amount of the power supply voltage supplied to the operational circuit and for delaying a clock signal which the second delay circuit section receives; a load circuit connected in parallel with the operating circuit to a common power supply wiring; and a phase detection section that detects a phase difference between the clock signal outputted from the first delay circuit section and the clock signal outputted from the second delay circuit section to control a consumed current amount consumed by the load circuit on the basis of the phase difference. COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于补偿由于操作电路的消耗电流的波动引起的电源电压变化的负载变化补偿电路。解决方案：提供了负载变化补偿电路，其包括：第一延迟电路部分，其延迟量被改变了提供给用于延迟时钟的操作电路的电源电压的每单位变化量的规定的第一变化量第一延迟电路部分接收的信号; 与第一延迟电路部并联制作的第二延迟电路部，其延迟量相对于提供给运算电路的电源电压的单位变化量而变化大于规定的第一变化量的规定的第二变化量，延迟第二延迟电路部分接收的时钟信号; 与工作电路并联连接到公共电源布线的负载电路; 以及相位检测部，其检测从第一延迟电路部输出的时钟信号与从第二延迟电路部输出的时钟信号之间的相位差，以基于相位差来控制负载电路消耗的消耗电流量。版权所有（C）2007，JPO＆INPIT

14. 发明专利

JP2007027285A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007027285A
公开(公告)日：2007-02-01
申请号：JP2005204968
申请日：2005-07-13
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU , WATANABE DAISUKE
IPC分类号： H01L21/822 , H01L21/82 , H01L27/04 , H03K5/15
摘要： PROBLEM TO BE SOLVED: To reduce SKEW and power consumption (AC component) dependent on operation in distribution of clock or data, and to suppress noise generated from a distribution circuit itself.
SOLUTION: The semiconductor device mounting a digital circuit 1a having one or more than one circuit blocks 10-1 through 10-n is provided with clock wiring 20 for distributing clock, and data wiring 30 for distributing data wherein the clock main path 21 of the clock wiring 20 has a clock buffer 25 connected between respective branch points of a clock branch path 22, and the data main path 31 of the data wiring 30 has a data buffer 35 connected between respective branch points of a data branch path 32. The semiconductor device is provided with bias wiring 40 for providing a BIAS signal to the clock buffer 25 and the data buffer 35, and a delay locked loop circuit (DLL) 60 generating the BIAS signal.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：根据时钟或数据分配中的操作减少SKEW和功耗（AC分量），并抑制从分配电路本身产生的噪声。解决方案：安装具有一个或多于一个电路块10-1至10-n的数字电路1a的半导体器件设置有用于分配时钟的时钟布线20和用于分发数据的数据布线30，其中时钟主路径 21个时钟布线20具有连接在时钟分支路径22的各分支点之间的时钟缓冲器25，数据线路30的数据主路径31具有连接在数据分支路径32的各个分支点之间的数据缓冲器35 半导体器件设置有用于向时钟缓冲器25和数据缓冲器35提供BIAS信号的偏置布线40以及产生BIAS信号的延迟锁定环电路（DLL）60。版权所有（C）2007，JPO＆INPIT

15. 发明专利

JP2005295165A Variable delay circuit 审中-公开
标题翻译：可变延迟电路
公开(公告)号：JP2005295165A
公开(公告)日：2005-10-20
申请号：JP2004106677
申请日：2004-03-31
申请人： Advantest Corp , 株式会社アドバンテスト
发明人： SUDA MASAKATSU
IPC分类号： G06F1/10 , H03K5/00 , H03K5/14
CPC分类号： G06F1/10 , H03K5/14
摘要： PROBLEM TO BE SOLVED: To provide a variable delay circuit in which a delay amount per stage is large and the delay amount is easily changeable. SOLUTION: This variable delay circuit is provided with signal wiring P1 for transmitting a pulse signal to be a delay target, an input buffer 10 and an output buffer 30 provided at an input side and an output side of the signal wiring P1, respectively, signal wiring P2 and P3 arranged adjacently to the signal wiring P1, and a delay set pulse generation circuit 20 for selectively inputting a in-phase or opposite phase pulse signal synchronized with timing at which the input buffer 10 inputs a pulse signal to the signal wiring P1 to the signal wiring P2 and P3. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种可变延迟电路，其中每级的延迟量大并且延迟量容易改变。解决方案：该可变延迟电路设置有用于发送作为延迟目标的脉冲信号的信号布线P1，设置在信号布线P1的输入侧和输出侧的输入缓冲器10和输出缓冲器30，分别与信号布线P1相邻布置的信号布线P2和P3，以及延迟设定脉冲生成电路20，用于选择性地输入与输入缓冲器10输入脉冲信号的定时同步的同相或反相脉冲信号信号线P1到信号线P2和P3。版权所有（C）2006，JPO＆NCIPI

16. 发明专利

JP2000314766A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000314766A
公开(公告)日：2000-11-14
申请号：JP2000019390
申请日：2000-01-27
申请人： ADVANTEST CORP
发明人： SUDA MASAKATSU
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319
摘要： PROBLEM TO BE SOLVED: To improve the yield of a semiconductor test by generating a test pattern for testing the action of a measured circuit, and outputting a measured result produced by the measured circuit when supplied with the test pattern, from an output terminal. SOLUTION: A pattern generating circuit 19 of this semiconductor device 52 generates a test pattern used to test the action of a measured circuit 32, and outputs a test result produced by the measured circuit 32, from a data output terminal 25. A controller 22 outputs a test period signal only by a predetermined cycle to the pattern generating circuit 19, and an oscillator 18 generates frequency clock used for a test and supplies it to the measured circuit 32. An oscillator controller 12 controls the frequency of the oscillator 18, and a clock selector 20 selects a supplied clock signal and supplies it to the measured circuit 32. A test can thereby be previously made in a practical frequency band in a preprocess, so that a rejected semiconductor can be removed prior to being sent to a following process.

17. 发明专利

JP2001033529A DELAY CLOCK GENERATOR AND SEMICONDUCTOR TESTER 失效
公开(公告)号：JP2001033529A
公开(公告)日：2001-02-09
申请号：JP2000141282
申请日：2000-05-15
申请人： ADVANTEST CORP
发明人： SUDA MASAKATSU
IPC分类号： G01R31/3183 , G06F1/06 , H03K5/135
摘要： PROBLEM TO BE SOLVED: To reduce a delay being generated from a high resolution delay section. SOLUTION: The delay clock generator 10 comprises a section 12 for generating a delay equal to an integer time of the period of a short reference clock and smaller than a specified delay, a section 40 for determining whether a delay equal to one half period of the reference clock is added to a delay generated from the period delay section 12 or not, and a high resolution delay section 16 for adding the difference between the delay generated from the period delay section 12 and the specified delay and the difference between the half period delay section 40 and the specified delay, respectively, to the delays generated from the period delay section 12 and the half period delay section 40.

18. 发明专利

JPH11205118A DIFFERENTIAL SIGNAL TRANSMISSION CIRCUIT 失效
公开(公告)号：JPH11205118A
公开(公告)日：1999-07-30
申请号：JP273298
申请日：1998-01-09
申请人： ADVANTEST CORP
发明人： SUDA MASAKATSU
IPC分类号： G06F3/00 , G01R31/319 , H03K19/0175 , H04L25/02
摘要： PROBLEM TO BE SOLVED: To directly drive a coaxial transmission line by providing a serial terminating circuit for serially terminating and matching the characteristic impedance of the transmission line by being directly inserted between a differential driver and the differential transmission line and including a prescribed impedance at a differential driver output point. SOLUTION: A matched termination circuit 31 is composed of an impedance matching part 31m and a serial terminating circuit 31st. The impedance matching pet 31m is composed of two resistors and a bypass capacitor, and the positive/negative output terminal of a differential driver and the circuit ground are connected by the impedance of prescribed resistance in the manner of high frequency. Therefore, an output impedance at the output terminal of the differential driver can be made into prescribed low impedance. Thus, by combining the serial terminating circuit 31st, impedance matching part 31m and differential driver, the serial termination can be matched with the transmission line and a high frequency component caused by a peaking circuit in the serial terminating circuit 31st can be compensated.

19. 发明专利

JPH10303709A PULSE WIDTH SHAPING CIRCUIT 失效
公开(公告)号：JPH10303709A
公开(公告)日：1998-11-13
申请号：JP10844797
申请日：1997-04-25
申请人： ADVANTEST CORP
发明人： SUDA MASAKATSU
IPC分类号： H03K5/06 , H03K3/017
摘要： PROBLEM TO BE SOLVED: To provide a pulse width shaping circuit in which the output timing of a shaped output pulse signal is stable by providing a gate means inhibiting the output of a delay pulse signal, when an input pulse signal exists and outputting the delay pulse signal when the input pulse signal does not exist. SOLUTION: In a pulse width differentiation circuit 40, a second delay element 2 receives a pulse signal Pc extended to prescribed pulse width by a pulse width integrating circuit 30 and supplies the pulse signal Pd delayed by the time of a prescribed delay quantity D1 to one input terminal of an AND gate 4., In the AND gate 4, the input pulse signal Pa is supplied to a negative input terminal, the delay pulse signal Pd is supplied to one input terminal, both signals are ANDed, and a pulse signal Pe which is shaped to prescribed width is outputted. The output pulse signal Pe is immediately outputted from the trailing edge position of the input pulse signal Pa, and the front edge of the output timing of the output pulse signal Pe is not at all affected by the delay of the first delay element 1.

20. 发明专利

JPH08320360A TIMING GENERATOR OF IC TESTER 失效
公开(公告)号：JPH08320360A
公开(公告)日：1996-12-03
申请号：JP12788395
申请日：1995-05-26
申请人： ADVANTEST CORP
发明人： SUDA MASAKATSU
IPC分类号： G01R31/3183 , G01R31/319 , H03K3/78 , H03K5/13 , H03K5/135
摘要： PURPOSE: To make stable against external fluctuation by minimizing the use of a high-accuracy delay means. CONSTITUTION: Pulses outputted by a rough timing generation means 1 13 is distributed to a set side delay means 26s and a reset side delay means 26r by a waveform generation control circuit 18 with a distributing means 17. Data Dr and Ds obtained by adding data which are equal to or less than T among measurement data from a memory 11, skew absorption data at the set side, and skew absorption data at the reset side are supplied to delay means 26s and 26r as delay control signals. Pulses where a logic delay means 27s is delayed by either 0, 1T, or 2T by a value which is equal to or more than T in the data Ds are supplied to an accurate delay means 28S and are delayed by a value which is equal to or less than T in the data Ds. Similarly, the pulses at the reset side which are equal to or more than T and equal to or less than T are delayed by an accurately delay means 28r by the data Dr. A flip flop 25 is set and reset by the output of the accurate delay means 28s and 28r, thus obtaining a wavefor m generation output.

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