专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

151. 发明专利

JPS5935222A Switching circuit 失效
标题翻译：切换电路
公开(公告)号：JPS5935222A
公开(公告)日：1984-02-25
申请号：JP14566182
申请日：1982-08-23
申请人： Nec Corp
发明人： MUTOU HIROSHI
IPC分类号： G06F13/366 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To obtain complex switching algorithm by simple circuits by providing a selecting circuit, fault detecting circuit, clock generating circuit, gate circuit, and counting circuit. CONSTITUTION:Input signals 1-8 are outputted selectively to an output terminal 10 through the selecting circuit (a). When the fault detecting circuit (b) detects the fault of the selected signal, the gate of the gate circuit (d) is opened and the counting circuit (e) counts a clock signal from the clock generating circuit (c). Its count result is supplied as a selection signal to the selecting circuit (a). Thus, the complex switching algorithm is formed by a simple circuit.
摘要翻译：目的：通过提供选择电路，故障检测电路，时钟发生电路，门电路和计数电路，通过简单的电路获得复杂的开关算法。构成：输入信号1-8通过选择电路（a）选择性地输出到输出端子10。当故障检测电路（b）检测到所选信号的故障时，门电路（d）的门断开，计数电路（e）对来自时钟发生电路（c）的时钟信号进行计数。其计数结果作为选择信号提供给选择电路（a）。因此，复合切换算法由简单的电路形成。

152. 发明专利

JPS5927360A Automatic reporting device of fault information 失效
标题翻译：自动报告故障信息
公开(公告)号：JPS5927360A
公开(公告)日：1984-02-13
申请号：JP13598482
申请日：1982-08-04
申请人： Mitsubishi Electric Corp
发明人： NISHIYAMA NOBORU
IPC分类号： G06F11/30 , G06F11/07
CPC分类号： G06F11/0703
摘要： PURPOSE:To constitute a titled device so that a person in charge of maintenance can grasp exactly contents of a fault and can execute quickly the maintenance service, by executing a repair work in case when repair can be executed, and giving information automatically in case when said work cannot be executed or the fault is continued, when the fault occurs. CONSTITUTION:When a fault occurs in a data processing system, a service processing device SVP4 detects it. Subsequently, internal state information of a CPU2, a main storage device MMU1 and an input/output processing device IOP3 at the point of time when the fault occurs is fetched, and whether the fault can be recovered or not is discriminated. If it can be recovered, the device SVP4 executes the recovery processing, continues the operation, puts an index by a fault information transfer program PGM9, and stores it in a file storage device FDD5. Also, in case when the fault cannot be recovered, or the fault exceeds a specified level even if it can be recovered, the device SVP4 transfers an alarm and fault information to a data receiving device APU8 through a public exchange circuit by a data transmitting device AXU6.
摘要翻译：目的：构成一个标题设备，使负责维护的人员可以掌握故障的内容，并可以快速执行维护服务，通过执行维修工作，如果可以执行维修，并在发生故障的情况下自动提供信息当故障发生时，所述工作不能执行或故障继续。构成：当数据处理系统发生故障时，服务处理装置SVP4检测到该故障。随后，取得故障发生时的CPU2，主存储装置MMU1以及输入输出处理装置IOP3的内部状态信息，判别故障是否可恢复。如果可以恢复，则设备SVP4执行恢复处理，继续操作，通过故障信息传送程序PGM9放置索引，并将其存储在文件存储设备FDD5中。此外，即使故障无法恢复，或故障超过指定级别即使可以恢复，设备SVP4通过数据发送设备通过公共交换电路将报警和故障信息传送到数据接收设备APU8 AXU6。

153. 发明专利

JPS5914059A Method for informing fault 失效
标题翻译：通知故障的方法
公开(公告)号：JPS5914059A
公开(公告)日：1984-01-24
申请号：JP12116382
申请日：1982-07-14
申请人： Fujitsu Ltd , Hitachi Ltd , Nec Corp , Nippon Telegr & Teleph Corp , Oki Electric Ind Co Ltd
发明人： IWAMOTO YOSHIHARU , KITANO HIROSHI , ENDOU AKIRA , ITOU TOSHINORI , FUKUI TOSHIMASA
IPC分类号： G06F11/30 , G06F11/07 , G06F13/00
CPC分类号： G06F11/0703
摘要： PURPOSE:To simplify a soft constitution, by classifying fault information into interruption causes to inform the classified results to a control device and reading out the details when necessary. CONSTITUTION:When data and status information ACOD=001 is returned from a processor PRC for control information sent from a control unit CNT, its answer data are temporarily stored in an answer data register 1. Subsequently, ''001'' is latched in an answer code register 2 and a buffer gate 5 is enabled by a decoder 3, so that the answer data are sent to the control unit CNT. The latch timing of the information is applied to the control device CNT. At the sending of control information, a timing circuit 4 is enabled by an EN input to supervise an ASYN signal. If the monitoring time is overflowed, an ISC signal is outputted through an OR gate 8. Detail fault information is stored in the answer code register 2.
摘要翻译：目的：为了简化软结构，将故障信息分类为中断原因，将分类结果通知给控制设备，并在必要时阅读详细信息。构成：当从控制单元CNT发送的控制信息的处理器PRC返回数据和状态信息ACOD = 001时，其应答数据被临时存储在应答数据寄存器1中。随后，将“001”锁存在应答码寄存器2和缓冲器门5由解码器3使能，使得应答数据被发送到控制单元CNT。信息的锁存定时被施加到控制装置CNT。在发送控制信息时，通过EN输入使能定时电路4来监视ASYN信号。如果监视时间溢出，则通过或门8输出ISC信号。详细故障信息存储在应答码寄存器2中。

154. 发明专利

JPS598064A Fault diagnosing system for multiplex computer system 失效
标题翻译：多重计算机系统故障诊断系统
公开(公告)号：JPS598064A
公开(公告)日：1984-01-17
申请号：JP11547782
申请日：1982-07-05
申请人： Toshiba Corp
发明人： OGIWARA SEI , HASEGAWA EIJI
IPC分类号： G06F11/16 , G06F11/07 , G06F15/16 , G06F15/177
CPC分类号： G06F11/0709 , G06F11/0703 , G06F11/073
摘要： PURPOSE:To prevent the loss of an important key for fault diagnosis of a multiplex computer, by collecting the information existing on a main memory of the series having a fault by means of remaining nondefective series. CONSTITUTION:If a fault arises to a computer of a series (a), the generation of the fault is informed to a CPU1b of a series (b). Receiving the information on the fault discontinuation of the series (a), a main memory information shunting program 2b-2 of the series (b) keeps the information existing on a main memory 2a of the series (a) in a main memory information preserving region 3b-2 of an external storage device (bulk memory) 3b of the series (b) via a signal system C and devices 5a and 5b. A CPU1a can give an access a main memory 2b of the remote system via the devices 5a and 5b. While the CPU1b can give an access to the memory 2a of the remote system via the devices 5b and 5a respectively.
摘要翻译：目的：为了防止多路复用计算机的故障诊断重要关键字的丢失，通过剩余的无缺陷序列收集存在故障序列的主存储器上的信息。构成：如果系列（a）的计算机发生故障，则将故障的产生通知给系列（b）的CPU1b。接收到系列（a）的故障中断的信息，（b）系列的主存储器信息分流程序2b-2将存储在系列（a）的主存储器2a上的信息保存在主存储器信息保存串联（b）的外部存储装置（大容量存储器）3b的区域3b-2经由信号系统C和装置5a和5b。 CPU1a可以经由设备5a和5b来访问远程系统的主存储器2b。而CPU1b可以分别经由设备5b和5a来访问远程系统的存储器2a。

155. 发明专利

JPS593610A Ipl retry processing system 失效
标题翻译： IPL重试处理系统
公开(公告)号：JPS593610A
公开(公告)日：1984-01-10
申请号：JP11332882
申请日：1982-06-30
申请人： Fujitsu Ltd
发明人： SAITOU TOSHIO
IPC分类号： G06F1/00 , G06F9/445 , G06F11/07 , G06F11/14
CPC分类号： G06F11/14 , G06F11/0703
摘要： PURPOSE:To redress an intermediate fault and a fixed fault of either of the 1st and the 2nd buses by providing the 1st and the 2nd buses each with an IPL equipment-item-number setting means and a retry frequency setting means for specifying the retry frequency of IPL processing. CONSTITUTION:Equipment item numbers and the frequency of IPL processing to be retried are set in IPL equipment-item-number setting registers 7 (specifying the 1st access bus) and 8 (specifying the 2nd access bus), and a retry frequency register 9 from a display console 6 or floppy disk 13 in advance. If abnormality occurs during processing, a +1 circuit 12 is operated until a retry counter 14 goes up to the contents of the retry frequency register 9 and then error information is collected when the counted value becomes equal to the contents of the register 9. A substitute bus execution counter 11 counts up by one and a decision on whether execution from a substitute bus is completed or not is made.
摘要翻译：目的：通过向第一和第二总线提供第一和第二总线来解决第一和第二总线中的中间故障和固定故障，每个总线分别具有IPL设备 - 项目号码设置装置和重试频率设置装置，用于指定重试频率的IPL处理。规定：在IPL设备 - 项目编号设置寄存器7（指定第一访问总线）和8（指定第二访问总线）中设置要重试的设备项目编号和IPL处理频率，以及重试频率寄存器9 显示控制台6或软盘13。如果在处理期间发生异常，则+1电路12被操作直到重试计数器14上升到重试频率寄存器9的内容，然后当计数值等于寄存器9的内容时收集错误信息。替代总线执行计数器11向上计数一个，并且作出关于从替代总线执行是否完成的决定。

156. 发明专利

JPS593607A Error processing system of channel 失效
标题翻译：通道错误处理系统
公开(公告)号：JPS593607A
公开(公告)日：1984-01-10
申请号：JP11356782
申请日：1982-06-30
申请人： Fujitsu Ltd
发明人： SHIMIZU SEIICHI , MOURI KOUJI
IPC分类号： G06F11/00 , G06F11/07 , G06F13/00
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To permit the use of other IOCs in case of error occurrence and to increase the availability of a system by providing a log analyzing means for analyzing fault information and an address outputting means for a selective resetting execution routine. CONSTITUTION:If an error occurs in a channel CH1 which is in normal data processing and coupled with an IOC2, an error detecting part 3 detects and reports the error occurrence to a log processing part 10 and a log collecting and analyzing part 11 analyzes it to place the CH1 in offline mode by an SVP. Then, the starting address BBB of the selective resetting execution routine is sent out to the CH1 and set in a PS address register 5. Consequently, connected IOCs except the IOC2 are permitted to be used by other channels. When it is judged that recovery from the error is impossible, an SPU causes a machine check interruption to a CPU and then the CH1 resets the IO system.
摘要翻译：目的：允许在发生错误时使用其他IOC，并通过提供用于分析故障信息的日志分析装置和用于选择性重置执行例程的地址输出装置来增加系统的可用性。构成：如果正常数据处理并与IOC2耦合的通道CH1发生错误，则错误检测部分3检测并向日志处理部分10报告错误发生，并且日志收集和分析部分11将其分析为由SVP将CH1置于离线模式。然后，选择性复位执行程序的起始地址BBB发送到CH1并设置在PS地址寄存器5中。因此，除了IOC2之外的连接的IOC被允许被其他通道使用。当判断出不可能从错误中恢复时，SPU会导致机器检查中断CPU，然后CH1复位IO系统。

157. 发明专利

JPS58211228A Data transfering system 失效
标题翻译：数据传输系统
公开(公告)号：JPS58211228A
公开(公告)日：1983-12-08
申请号：JP9553582
申请日：1982-06-03
申请人： Nec Corp
发明人： KATAKURA HIDEO
IPC分类号： G06F11/22 , G06F11/07 , G06F13/00
CPC分类号： G06F11/0703
摘要： PURPOSE:To shorten a fault releasing time, by providing a system monitoring device and an automatic switching device, detecting and displaying the existence of a fault of each device in a system, and also connecting automatically a terminal equipment to other terminal controller when a fault occurs. CONSTITUTION:Plural terminal line controllers 3, 4 are connected to a computer 2 for controlling the whole system, and plural POS terminals 101-10n, 201-20n are connected to each controller 3, 4 through an automatic switching device 5. A system monitoring device 1 is connected to a device monitoring signal line 6 of this computer and the respective device monitoring signal lines 7, 8 of the controllers 3, 4, and the presence of a fault of the controllers 3, 4 and the terminal equipments 101-10n, 201-20n is detected. Subsequently, the result of detection is displayed on a terminal state display part, also when a fault occurs, relays 20, 21 of the device 5 are driven, and connection of the controllers 3, 4 and the terminal equipments 101-10n, 201-20n is switched automatically to the normal side.
摘要翻译：目的：通过提供系统监控设备和自动切换设备来缩短故障释放时间，检测和显示系统中每个设备故障的存在，并在故障时自动将终端设备连接到其他终端控制器发生。构成：多个终端线路控制器3,4连接到用于控制整个系统的计算机2，并且多个POS终端101-10n，201-20n通过自动切换装置5连接到每个控制器3,4。设备1连接到该计算机的设备监视信号线6和控制器3,4的相应设备监视信号线7,8，并且存在控制器3,4和终端设备101-10n的故障，201-20n被检测到。随后，在终端状态显示部分上显示检测结果，并且当故障发生时，设备5的继电器20,21被驱动，控制器3,4与终端设备101-10n，201- 20n自动切换到正常侧。

158. 发明专利

JPS58185100A Semiconductor external storage controller 失效
标题翻译：半导体外部存储控制器
公开(公告)号：JPS58185100A
公开(公告)日：1983-10-28
申请号：JP6893682
申请日：1982-04-24
申请人： Toshiba Corp
发明人： KANEKO YASUO
IPC分类号： G06F12/16 , G06F11/07
CPC分类号： G06F11/0727 , G06F11/0703
摘要： PURPOSE:To prevent the generation of an incidental accident at an address having a low frequency of access and to improve reliability of the titled controller, by performing the correction and rewriting of the reading data through all addresses of an external storage device in an idle time during which no data is transferred from a central processor. CONSTITUTION:An external storage controller 2 checks a command given from a main body. In case no command is checked, the controller 2 transmits a reading request to an external storage device via a signal line 26 by an address register 22 which is previously set and performs the reading and data checking. Then a 1-bit error if detected is corrected, and the writing is carried out again to the same address. In such a way, an incidental accident of a system can be previously prevented to improve the reliability.
摘要翻译：目的：为了防止在具有低访问频率的地址上产生意外事故并提高标题控制器的可靠性，通过在空闲时间内通过外部存储设备的所有地址执行读取数据的校正和重写在此期间没有数据从中央处理器传输。构成：外部存储控制器2检查从主体给出的命令。如果未检查命令，则控制器2经由信号线26通过预先设定的地址寄存器22向外部存储装置发送读取请求，并执行读取和数据检查。然后如果检测到1位错误被更正，并且写入再次执行到相同的地址。以这种方式，可以防止系统的偶然事故提高可靠性。

159. 发明专利

JPS58184662A Storage device 失效
标题翻译：储存设备
公开(公告)号：JPS58184662A
公开(公告)日：1983-10-28
申请号：JP6687782
申请日：1982-04-21
申请人： Fujitsu Ltd
发明人： OGASAWARA YASUO , IZAWA EIICHI
IPC分类号： G06F12/16 , G06F11/07 , G06F11/16
CPC分类号： G06F11/0727 , G06F11/0703
摘要： PURPOSE:To prevent a fault of a storage device from exerting great influence upon the operation of an information processing system, by providing each storage device with a means for controlling the writing of data. CONSTITUTION:Each one of main storage devices MM0 and MM1 consist of a storage unit MU and various control circuits. The storage units MU of the main storage devices MM0 and MM1 are accessible from a central controller CC. The main storage devices MM0 and MM1 are provided with mode setting flip-flops AF respectively. The mode setting flip-flop AF of a main storage device in living operation mode is set by a setting signal ST from the central controller CC and the mode setting flip-flop AF of the other main storage device in stand- by operation mode is reset by a resetting signal RS from the central controller CC.
摘要翻译：目的：为了防止存储设备的故障对信息处理系统的操作产生很大的影响，通过为每个存储设备提供控制数据写入的装置。构成：主存储装置MM0和MM1中的每一个由存储单元MU和各种控制电路组成。主存储装置MM0和MM1的存储单元MU可从中央控制器CC访问。主存储装置MM0和MM1分别设置有模式设置触发器AF。生活操作模式下的主存储装置的模式设置触发器AF由来自中央控制器CC的设定信号ST设定，另一个主存储装置的模式设定触发器AF在待机操作模式下被复位通过来自中央控制器CC的复位信号RS。

160. 发明专利

JPS58181130A Error processing system 失效
标题翻译：错误处理系统
公开(公告)号：JPS58181130A
公开(公告)日：1983-10-22
申请号：JP6317882
申请日：1982-04-15
申请人： Fujitsu Ltd
发明人： OJIRO YOSHIFUMI , KATOU TAKAO
IPC分类号： G06F11/30 , G06F11/07 , G06F13/00
CPC分类号： G06F11/0745 , G06F11/0703
摘要： PURPOSE:To improve the reliability and the throughput with simple constitution, by transmitting a specific error signal to a request source in accordance with the discrimination of the detection result of a counter. CONSTITUTION:A data register 50 and an ID register 51 are registers on the request input side, and contents of the register 51 are inputted to a processing part 59 and a monitor controlling block 54 through a bus 61. In this block 54, a processing request having ID is accepted and stored, and the lapse of a certain time is detected by the counter. The occurrence of an error in the request having ID is detected by generating a signal again from the counter. This signal is sent to a selecting circuit 55 by an encoder 57. This circuit 55 not only puts the output of a channel ID, where the error occurs, onto an ID bus 62 bus also puts contents of an error code register 58 onto a bus 67 from a selecting circuit 56 to transmit the error signal including ID to the request source.
摘要翻译：目的：通过简单的结构提高可靠性和吞吐量，根据对计数器的检测结果的区分，将特定的错误信号发送到请求源。构成：数据寄存器50和ID寄存器51被寄存在请求输入侧，寄存器51的内容通过总线61输入到处理部分59和监视器控制块54.在该方框54中，处理请求ID被接收和存储，并且计数器检测到一定时间的流逝。通过从计数器再次产生信号来检测具有ID的请求中的错误的发生。该信号由编码器57发送到选择电路55.该电路55不仅将错误发生的信道ID的输出放在ID总线62总线上，还将错误代码寄存器58的内容放在总线上从选择电路56输出包含ID的错误信号到请求源。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式