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121. 发明专利

JP2012038965A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2012038965A
公开(公告)日：2012-02-23
申请号：JP2010178744
申请日：2010-08-09
申请人： Lapis Semiconductor Co Ltd , ラピスセミコンダクタ株式会社
发明人： KOMORI KENJI
IPC分类号： H01L21/768 , H01L21/318
CPC分类号： H01L24/11 , C23C16/345 , C23C16/5096 , C23C16/517 , H01L21/0217 , H01L21/02274 , H01L21/31116 , H01L21/76801 , H01L21/76804 , H01L23/3171 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/0345 , H01L2224/03912 , H01L2224/0401 , H01L2224/05013 , H01L2224/05022 , H01L2224/05027 , H01L2224/05124 , H01L2224/05155 , H01L2224/05166 , H01L2224/05184 , H01L2224/05572 , H01L2224/05644 , H01L2224/1145 , H01L2224/11462 , H01L2224/11464 , H01L2224/1147 , H01L2224/13022 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01088 , H01L2924/01327 , H01L2924/1306 , H01L2924/14 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of controlling a dimension of a connection hole side wall in an insulator film with high accuracy and at low cost.SOLUTION: The semiconductor device 1 includes an insulator film 12 coating the principal plane of a substrate 10 and having a connection hole 12h which reaches a top face of a bottom electrode 11. A film density of the insulator film 12 reduces as departing from the principal plane of the substrate 10 in a thickness direction of the insulator film 12. Inner diameter of the connection hole 12h enlarges as the film density of the insulator film 12 reduces.
摘要翻译：解决的问题：提供能够以高精度和低成本控制绝缘膜中的连接孔侧壁的尺寸的半导体器件。解决方案：半导体器件1包括涂覆基板10的主平面并具有到达底部电极11的顶面的连接孔12h的绝缘膜12.绝缘膜12的膜密度随着离开而减小从绝缘膜12的厚度方向的基板10的主平面延伸。连接孔12h的内径随着绝缘膜12的膜密度的减小而扩大。版权所有（C）2012，JPO＆INPIT

122. 发明专利

JP2012033796A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2012033796A
公开(公告)日：2012-02-16
申请号：JP2010173435
申请日：2010-08-02
申请人： Panasonic Corp , パナソニック株式会社
发明人： HIRANO HIROSHIGE , OTA YUKITOSHI , ITO YUTAKA
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L21/76807 , H01L23/528 , H01L24/03 , H01L24/05 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05017 , H01L2224/05093 , H01L2224/05546 , H01L2224/05551 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05624 , H01L2224/48453 , H01L2224/48463 , H01L2224/85205 , H01L2924/00014 , H01L2924/00012 , H01L2924/00 , H01L2224/45099
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device including a pad structure without dishing and void free which is stably formed in a short time.SOLUTION: The semiconductor device comprises a pad including a plurality of pad lines 109p on a first insulator film 108B formed on a substrate 100. A second insulator film 110 having an opening disposed above at least a part of the pad is formed on the first insulator film 108B. A line connection part 109q is provided for electrically connecting neighboring lines among the plurality of pad lines 109p. A width W1 of each pad line 109p is smaller than a height of each pad line 109p and larger than a width W3 of the line connection part 109q.
摘要翻译：解决的问题：提供一种半导体器件，其包括在短时间内稳定形成的无凹陷和无空隙的焊盘结构。解决方案：半导体器件包括在形成于衬底100上的第一绝缘膜108B上包括多个衬垫线109p的焊盘。在第二绝缘膜110上形成具有设置在衬垫的至少一部分上方的开口的第二绝缘膜110形成在第一绝缘膜108B。线连接部109q用于电连接多条衬垫线109p中的相邻线。每个衬垫线109p的宽度W1小于每个衬垫线109p的高度并且大于线连接部109q的宽度W3。版权所有（C）2012，JPO＆INPIT

123. 发明专利

JP2012028795A Method and system for reinforcing bond pad 有权
标题翻译：用于增强粘结垫的方法和系统
公开(公告)号：JP2012028795A
公开(公告)日：2012-02-09
申请号：JP2011197816
申请日：2011-09-12
申请人： Agere Systems Inc , アギアシステムズインコーポレーテッド
发明人： MARK ADAM BACHMAN , DANIEL PATRICK CHESIRE , MERCHANT SAILESH M , JOHN WILLIAM OSENBACH , KURT GEORGE STINNEY
IPC分类号： H01L21/60 , H01L23/52 , H01L21/3205 , H01L23/00 , H01L23/485
CPC分类号： H01L24/05 , H01L21/768 , H01L23/562 , H01L24/03 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05093 , H01L2224/05558 , H01L2224/05567 , H01L2224/05624 , H01L2224/05647 , H01L2924/00014 , H01L2924/0002 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To avoid or reduce occurrence of defects of a probe and bonding.SOLUTION: A reinforcing system and a reinforcing method for reinforcing a contact pad of an integrated circuit are disclosed. Particularly a system and a method which include a reinforced structure inserted between an upper contact pad layer and a lower metallic layer are exemplified.
摘要翻译：要解决的问题：避免或减少探针和接合缺陷的发生。解决方案：公开了一种用于加强集成电路的接触焊盘的增强系统和加强方法。特别地，示例了包括插入在上接触焊盘层和下金属层之间的增强结构的系统和方法。版权所有（C）2012，JPO＆INPIT

124. 发明专利

JP2012028708A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2012028708A
公开(公告)日：2012-02-09
申请号：JP2010168686
申请日：2010-07-27
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： MATSUI SATOSHI , EDA TAKESHI , MATSUMOTO AKIRA , KYOGOKU YOSHITAKA , WATANABE SHINJI , HONDA HIROKAZU
IPC分类号： H01L23/12 , H01L21/3205 , H01L23/52
CPC分类号： H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/03462 , H01L2224/0401 , H01L2224/05567 , H01L2224/05647 , H01L2224/11462 , H01L2224/11622 , H01L2224/11849 , H01L2224/13007 , H01L2224/13022 , H01L2224/13147 , H01L2224/1354 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01075 , H01L2924/01082 , H01L2924/014 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To effectively relax the stress applied to a semiconductor chip via a flip-chip bump.SOLUTION: A semiconductor device 200 comprises: an interconnection 210 formed on a semiconductor chip 202; a first insulating film (214) that is formed above the interconnection 210 and has a first opening 214a; a pad electrode film 216 formed in contact with the interconnection 210; a second insulating film (218) that is formed above the pad electrode film 216 and has a second opening 218a; and a flip-chip bump 220 formed in contact with the pad electrode film 216. In a plan view, the second insulating film exists between the flip-chip bump and the pad electrode film 216 in a region right below an outer edge of the flip-chip bump 220. The outer edge of the flip-chip bump 220 is formed in a region inside an outer edge of the pad electrode film 216.
摘要翻译：要解决的问题：通过倒装芯片凸块有效地缓解施加到半导体芯片的应力。解决方案：半导体器件200包括：形成在半导体芯片202上的互连210; 第一绝缘膜（214），其形成在互连210上方并具有第一开口214a; 形成为与互连件210接触的焊盘电极膜216; 第二绝缘膜（218），其形成在焊盘电极膜216的上方并具有第二开口218a; 以及形成为与焊盘电极膜216接触的倒装凸块220.在平面图中，第二绝缘膜存在于倒装芯片凸块和焊盘电极膜216之间的位于翻盖的外边缘的正下方的区域中倒装芯片凸块220的外边缘形成在焊盘电极膜216的外边缘内的区域中。（C）2012年，JPO和INPIT

125. 发明专利

JP2012015551A Method of manufacturing self-aligning wafer or chip structure 有权
标题翻译：自制波形或芯片结构的制造方法
公开(公告)号：JP2012015551A
公开(公告)日：2012-01-19
申请号：JP2011221320
申请日：2011-10-05
申请人： Ind Technol Res Inst , 財団法人工業技術研究院Industrial Technology Research Institute
发明人： CHEN JUNG-TAI , HO TZONG-CHE , CHU JUN-HUN
IPC分类号： H01L25/065 , H01L21/3205 , H01L23/12 , H01L23/52 , H01L25/07 , H01L25/18
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/11 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02311 , H01L2224/02313 , H01L2224/0401 , H01L2224/05025 , H01L2224/05147 , H01L2224/0557 , H01L2224/05647 , H01L2224/13025 , H01L2224/13099 , H01L2224/16146 , H01L2224/16147 , H01L2224/2518 , H01L2224/81136 , H01L2224/81801 , H01L2225/0652 , H01L2225/06541 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/30107 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a self-aligning wafer or a chip structure equipped with a substrate, at least one first recessed base portion, at least one second recessed base portion, at least one connecting structure, and at least one bump.SOLUTION: A substrate 100 has a first surface 101a and a second surface 101b, and at least one pad 102 is formed on the first surface 101a. A first recessed base portion 116 is disposed on the first surface 101a, and electrically connected to the pad 102. A second recessed base portion 120 is disposed on the second surface 101b. A connecting structure penetrates the substrate 100 so as to be electrically connected to the first and second recessed base portions 116 and 120, and is disposed between the first and second recessed base portions 116 and 120. A bump 122 is filled in the second recessed base portion 120, and projects out from the second surface 101b.
摘要翻译：要解决的问题：提供一种配置有基板的自对准晶片或芯片结构，至少一个第一凹入基部，至少一个第二凹入基部，至少一个连接结构和至少一个连接结构磕碰。解决方案：基板100具有第一表面101a和第二表面101b，并且至少一个焊盘102形成在第一表面101a上。第一凹入基部116设置在第一表面101a上并电连接到垫102.第二凹入基部120设置在第二表面101b上。连接结构穿透基板100以电连接到第一和第二凹入基部116和120，并且设置在第一和第二凹入基部116和120之间。凸块122填充在第二凹入基部部分120，并从第二表面101b突出。版权所有（C）2012，JPO＆INPIT

126. 发明专利

JP2012009822A Semiconductor device and semiconductor device unit 有权
标题翻译：半导体器件和半导体器件单元
公开(公告)号：JP2012009822A
公开(公告)日：2012-01-12
申请号：JP2011064513
申请日：2011-03-23
申请人： Panasonic Corp , パナソニック株式会社
发明人： NAKANO SUMIAKI
IPC分类号： H01L21/60
CPC分类号： H01L24/11 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/73 , H01L2224/0345 , H01L2224/0346 , H01L2224/03903 , H01L2224/0401 , H01L2224/05556 , H01L2224/05558 , H01L2224/05571 , H01L2224/05572 , H01L2224/05655 , H01L2224/10145 , H01L2224/11318 , H01L2224/1132 , H01L2224/1146 , H01L2224/11849 , H01L2224/13021 , H01L2224/13022 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2224/13155 , H01L2224/16225 , H01L2224/73204 , H01L2224/93 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01084 , H01L2924/014 , H01L2224/11 , H01L2924/00 , H01L2924/00012 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device provided with a structure preventing a large protrusion of a bump from a metal layer as much as possible.SOLUTION: The semiconductor device comprises a substrate 12, a plurality of electrode pads 20 formed on the substrate 12, and a protection film 14 formed to cover peripheral edges of the electrode pads 20 and the substrate 12 and having through-holes 16 formed corresponding the respective electrode pads 20. An inner wall of each through-hole 16 is formed on a slant 22 toward the outside of the through-hole 16. A metal layer 24 is formed on an exposed surface of the electrode pads 20 exposed from the protection film 14 via the through-hole 16 and to the middle of the slant 22 of the through-hole 16. A bump 18 is bonded to a metal layer 22.
摘要翻译：解决的问题：提供一种半导体器件，其设置有尽可能防止凸起从金属层的大突起的结构。解决方案：半导体器件包括基板12，形成在基板12上的多个电极焊盘20以及形成为覆盖电极焊盘20和基板12的周边边缘并具有通孔16的保护膜14 形成对应于各个电极焊盘20.每个通孔16的内壁形成在倾斜22上，朝向通孔16的外侧。金属层24形成在暴露于电极焊盘20的暴露表面上保护膜14通过通孔16和通孔16的倾斜22的中间。凸块18接合到金属层22上。（C）2012，JPO和INPIT

127. 发明专利

JP2012004210A Semiconductor integrated circuit device and method of manufacturing the same 有权
标题翻译：半导体集成电路装置及其制造方法
公开(公告)号：JP2012004210A
公开(公告)日：2012-01-05
申请号：JP2010136029
申请日：2010-06-15
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SHIGIHARA HIROMI , YAJIMA AKIRA , SHIGIHARA HISAO , TSUKAMOTO HIROSHI
IPC分类号： H01L23/52 , H01L21/3205 , H01L23/12
CPC分类号： H01L23/53238 , H01L23/525 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/02331 , H01L2224/02379 , H01L2224/02381 , H01L2224/0401 , H01L2224/04042 , H01L2224/05024 , H01L2224/05073 , H01L2224/05166 , H01L2224/05187 , H01L2224/05553 , H01L2224/05568 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/13023 , H01L2224/13099 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48095 , H01L2224/48247 , H01L2224/48465 , H01L2224/48624 , H01L2224/48644 , H01L2224/48724 , H01L2224/48844 , H01L2224/85207 , H01L2224/85399 , H01L2924/0001 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0496 , H01L2924/10162 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/181 , H01L2924/04941 , H01L2924/04953 , H01L2224/48824 , H01L2924/00 , H01L2224/48744 , H01L2924/00012 , H01L2224/05552 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To suppress peeling of Au pads for external connection provided on rewiring which is mainly composed of Cu.SOLUTION: On the surface of rewiring 15 consisting of a two-layer film where a Ni film 15b is laminated on a Cu film 15a, a pad 18 to be connected with a wire is formed. The pad 18 consists of a two-layer film where an Au film 19b is laminated on a Ni film 19a, and is formed integrally to cover the top face and the side face of the rewiring 15. Since the contact area of the rewiring 15 and the pad 18 increases, the pad 18 is not peeled off from the rewiring 15 easily.
摘要翻译：要解决的问题：抑制主要由Cu组成的重新布线所提供的用于外部连接的Au焊盘的剥离。解决方案：在由Cu膜15a上层压有Ni膜15b的两层膜构成的再布线15的表面上形成与导线连接的焊盘18。垫18由两层膜组成，其中Au膜19b层叠在Ni膜19a上，并且整体形成以覆盖重新布线15的顶面和侧面。由于重新布线15的接触面积和垫18增加，垫18不容易从再布线15剥离。版权所有（C）2012，JPO＆INPIT

128. 发明专利

JP2011258687A Semiconductor device and method of manufacturing the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011258687A
公开(公告)日：2011-12-22
申请号：JP2010130835
申请日：2010-06-08
申请人： Renesas Electronics Corp , ルネサスエレクトロニクス株式会社
发明人： SUEYOSHI MANABU , MURANAKA MASASHI , SHONO TOMOTAKA , SUGANO ITARU
IPC分类号： H01L27/00 , H01L21/3205 , H01L21/822 , H01L23/52 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/04
CPC分类号： H01L25/0657 , H01L21/76898 , H01L23/3128 , H01L23/481 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/73 , H01L24/83 , H01L24/92 , H01L25/0652 , H01L25/50 , H01L2224/0401 , H01L2224/04042 , H01L2224/05009 , H01L2224/05017 , H01L2224/05554 , H01L2224/0557 , H01L2224/056 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/13111 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/48229 , H01L2224/73204 , H01L2224/73215 , H01L2224/73257 , H01L2224/73265 , H01L2224/83005 , H01L2224/9202 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06544 , H01L2225/06558 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10162 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00012 , H01L2924/00011 , H01L2224/05552 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device, in which semiconductor substrates to be stacked are put in good electrical connection with each other by a conductor embedded in a through-hole.SOLUTION: The semiconductor device includes a stack of semiconductor substrates. The first semiconductor substrate SCP includes: a base SUB having principal surfaces; a semiconductor element TR formed in and on the base SUB; wiring MTL electrically connected with the semiconductor element TR; and a conductive layer TSV formed inside a through-hole extending through first and second principal faces forming the principal surfaces of the base SUB and opposed to each other to the wiring MTL. The second semiconductor substrate SCP is stacked on the first semiconductor substrate SCP with the conductive layer TSV electrically connected with the wiring MTL of the second semiconductor substrate SCP. In the second principal face of the conductive layer TSV, a concavity portion DUM is formed around an end of the through-hole and a bottom wall face of the concavity portion DUM is located in the base SUB. The inside of the concavity portion DUM is filled with conductive material CU constituting the conductive layer TSV.
摘要翻译：要解决的问题：提供一种半导体器件，其中待堆叠的半导体衬底通过嵌入通孔中的导体彼此良好地电连接。解决方案：半导体器件包括一叠半导体衬底。第一半导体衬底SCP包括：具有主表面的基底SUB; 形成在基底SUB中和之上的半导体元件TR; 接线MTL与半导体元件TR电连接; 以及形成在贯穿第一和第二主面的通孔内的导电层TSV，所述第一和第二主面形成基部SUB的主表面并且彼此相对于布线MTL。第二半导体衬底SCP堆叠在第一半导体衬底SCP上，导电层TSV与第二半导体衬底SCP的布线MTL电连接。在导电层TSV的第二主面中，在通孔的端部周围形成凹部DUM，凹部DUM的底壁面位于基部SUB中。凹部DUM的内部填充有构成导电层TSV的导电性材料CU。版权所有（C）2012，JPO＆INPIT

129. 发明专利

JP2011258662A Method of manufacturing semiconductor device and semiconductor device 有权
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：JP2011258662A
公开(公告)日：2011-12-22
申请号：JP2010130412
申请日：2010-06-07
申请人： Shindengen Electric Mfg Co Ltd , 新電元工業株式会社
发明人： OGASAWARA ATSUSHI , MATSUZAKI KINSHI
IPC分类号： H01L29/861 , H01L21/28 , H01L21/329 , H01L29/47 , H01L29/872
CPC分类号： H01L29/872 , H01L2224/04042 , H01L2224/05567 , H01L2224/06181 , H01L2924/0002 , H01L2924/12032 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device, with a MPS structure, capable of reducing leakage current in reverse characteristics.SOLUTION: A semiconductor device comprises an ohmic junction part in which a semiconductor of a first conductive type and a metal layer are ohmically contacted, and a Schottky junction part in which a semiconductor of a second conductive type and the metal layer are Schottky-connected. The method of manufacturing the semiconductor device comprises: metal layer formation steps (steps S101 and S102) of forming the metal layer by thining the film thickness of the ohmic junction part in a film thickness range capable of performing ohmic junction; insulating film formation steps (steps S103 and S104) of forming an insulating film covering a part of the metal layer for protection; and a heat treatment step (step S105) of baking the insulating film and siliciding the metal layer of the ohmic junction part after the insulating film formation steps (steps S103 and S104).
摘要翻译：解决的问题：提供一种具有MPS结构的半导体器件的制造方法，能够减少反向特性的漏电流。解决方案：半导体器件包括欧姆接合部分，其中第一导电类型和金属层的半导体被欧姆接触，以及肖特基接合部分，其中第二导电类型和金属层的半导体是肖特基 -连接的。制造半导体器件的方法包括：通过在能够进行欧姆接合的膜厚度范围内使欧姆接合部的膜厚度形成金属层的金属层形成步骤（步骤S101和S102）绝缘膜形成步骤（步骤S103和S104），形成覆盖用于保护的金属层的一部分的绝缘膜; 以及在绝缘膜形成步骤之后烘烤绝缘膜并使欧姆接合部分的金属层硅化的热处理步骤（步骤S105）（步骤S103和S104）。版权所有（C）2012，JPO＆INPIT

130. 发明专利

JP2011249563A Semiconductor device and manufacturing method of the same 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：JP2011249563A
公开(公告)日：2011-12-08
申请号：JP2010121313
申请日：2010-05-27
申请人： Panasonic Corp , パナソニック株式会社
发明人： AOI NOBUO
IPC分类号： H01L23/52 , H01L21/3205
CPC分类号： H01L23/3677 , H01L23/29 , H01L23/3171 , H01L23/481 , H01L24/05 , H01L24/06 , H01L24/13 , H01L24/16 , H01L2224/02372 , H01L2224/0401 , H01L2224/05009 , H01L2224/05548 , H01L2224/05567 , H01L2224/05568 , H01L2224/05569 , H01L2224/0557 , H01L2224/05647 , H01L2224/06181 , H01L2224/13009 , H01L2224/13022 , H01L2224/13024 , H01L2224/13025 , H01L2224/131 , H01L2224/16145 , H01L2224/94 , H01L2924/0002 , H01L2924/14 , H01L2924/1431 , H01L2924/014 , H01L2224/81 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device and manufacturing method of the same having high heat dissipation efficiency, which achieves an enough heat dissipation effect even when three-dimensional integration technology is applied.SOLUTION: A first concavity 3 where at least an end face of a through electrode 2 is exposed and a second concavity 8 where the through electrode 2 is not exposed are formed on a surface 1b opposite to an element formation surface of a semiconductor substrate 1. A first insulation film 4 is formed on the surface 1b of the semiconductor substrate 1 so as to cover an inner surface of the first concavity 3 except the end face of the through electrode 2, and to cover an inner surface of the second concavity 8. A conductive film 5 that connects with the end face of the through electrode 2 and extends to the outside of the first concavity 3 is formed on the first insulation film 4.
摘要翻译：要解决的问题：提供一种具有高散热效率的半导体器件及其制造方法，即使应用三维集成技术也能够获得足够的散热效果。解决方案：在与半导体的元件形成表面相对的表面1b上形成有通孔2的至少端面露出的第一凹部3和未暴露贯通电极2的第二凹部8 基板1.在半导体基板1的表面1b上形成第一绝缘膜4，以覆盖除通孔2的端面之外的第一凹部3的内表面，并且覆盖第二绝缘膜4的内表面在第一绝缘膜4上形成有与贯通电极2的端面连接并延伸到第一凹部3的外侧的导电膜5.版权所有（C）2012，JPO＆INPIT

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