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91. 发明专利

JPH06150660A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06150660A
公开(公告)日：1994-05-31
申请号：JP3505493
申请日：1993-02-24
申请人： MITSUBISHI ELECTRIC CORP
发明人： SUGA YASUHIRO
IPC分类号： G11C11/41 , G11C7/12 , G11C7/22 , G11C8/18 , G11C11/409
摘要： PURPOSE:To perform reading operation at high speed. CONSTITUTION:A voltage applying control circuit 21 fetches the ATD control signal S7 of an ATD control circuit 7 and the output signal OUT of an output buffer 6 and outputs a control signal S21 based on the output signal OUT to a voltage applying circuit 22 in a period in which the ATD control signal S7 is on an H level. The voltage applying circuit 22 applies a voltage on a bit line 5 BL and '-' BL based on a control signal S21 so that the bit line pair BL, '-' BL is equalized in a shorter period. Consequently, since the equalizing processing is performed at high speed, reading operation is performed at high speed so much.

92. 发明专利

JPH06111597A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH06111597A
公开(公告)日：1994-04-22
申请号：JP25505892
申请日：1992-09-24
申请人： NEC CORP
发明人： ITO MUNEHIRO
IPC分类号： G11C11/41 , G11C8/18 , G11C11/413 , G11C29/00 , G11C29/04
摘要： PURPOSE:To activate a selected redundancy address switch at high speed and to shorten address access time by using a signal of an input side of a logic circuit as a pre-charge signal of a redundancy decoder and performing pre- charge quickly. CONSTITUTION:A redundancy decoder (RD) and address buffer groups 10, 11 specifying a reading address are provided on an information reading circuit of a buffer group 13. ATD circuits A 20 and B 21 connected to these buffer groups 10, 11 detect variation of an address signal and the outputted detected output ATDA and B are integrated by a NAND gate 23. Further, a signal of an input side of a gate 23 is used as a pre-charge signal of the RD, a transistor 52 is added in parallel to a (p) type transistor 51 of ATD input, and each input is made ATDA and B of two stages before ATD. Thereby, precharge of RD is quickly performed, the selected redundancy address switches are activated at high speed and address access time is shortened.

93. 发明专利

JPH05274869A 失效
公开(公告)号：JPH05274869A
公开(公告)日：1993-10-22
申请号：JP6695992
申请日：1992-03-25
IPC分类号： G11C11/41 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406
摘要： PURPOSE:To reduce the load requesting to an external circuit for an initialization by providing a selective imparting means imparting an internal. clock pulse to an initializing control means till a prescribed time passes after power source voltage starts to supply. CONSTITUTION:A dummy clock signal generator 1 receives power source voltage Vcc and generates a dummy clock signal Sa of a prescribed frequency. A timer circuit 2 receives the power source voltage Vcc, detects the lapse of preliminarily fixed time and outputs a switching control means Sb for controlling a switching circuit 3. The switching circuit 3 receives a signal/RAS to be given from the outside and a signal Sa of the dummy clock signal generator 1. The switching circuit 3 responses to a switching control signal Sb of the timer circuit 2 and imparts one of the signal/RAS and Sa as an output signal Sc to a clock signal generator 51.

94. 发明专利

JPH0550775B2 失效
公开(公告)号：JPH0550775B2
公开(公告)日：1993-07-29
申请号：JP30162186
申请日：1986-12-19
申请人： FUJITSU LTD
发明人： IHI TAKASHI
IPC分类号： G06F12/00 , G11C7/22 , G11C8/18

95. 发明专利

JPH05101665A ADDRESS-TRANSITION DETECTING CIRCUIT 失效
公开(公告)号：JPH05101665A
公开(公告)日：1993-04-23
申请号：JP7703692
申请日：1992-03-31
申请人： SAMSUNG ELECTRONIC
发明人： BONNKIYON KIMU , UNNMU RII
IPC分类号： G11C11/41 , G11C8/18 , G11C16/02 , G11C17/00
摘要： PURPOSE: To provide an address transition detection circuit for not causing malfunctions even when an address is shifted in a long time in a semiconductor memory device for performing the address floating of an SRAM and a ROM, etc. CONSTITUTION: The output of an address buffer is inputted to the input means 101 and 102 of a high trip level and a low trip level and the outputs of the input means 101 and 102 are respectively inputted to inverters provided with resistance elements 75 and 78 and capacitors 80 and 81. Then, the respective outputs of the inverters are impressed to the gates of transistors M1 and M2 and pulses are generated on the output line of an ATD.

96. 发明专利

JPH04298888A ADDRESS TRANSITION DETECTING CIRCUIT 失效
公开(公告)号：JPH04298888A
公开(公告)日：1992-10-22
申请号：JP31611891
申请日：1991-11-29
申请人： HYUNDAI ELECTRONICS IND
发明人： YON HEE KIMU , HON SEOKU KIMU
IPC分类号： G11C11/41 , G11C8/18
摘要： PURPOSE: To prevent the consumption of power by interrupting a current route during the generation of an address shift detection pulse. CONSTITUTION: An address Ai becomes an L level, the output terminals a' of an invertor G12 and the output terminal b' of an invertor G14 become H levels, an n-channel MOSFET MN 6 is turned on and ATD becomes a low state in a state where the current circuit from a power source Vcc to an address shift detection signal (ATD) is interrupted. The address Ai is shifted to the H level, the output terminals a' and b' become the L levels, the n-channel MOSFET MN5 and MN6 are turned off and ATD generates the pulse of the high state. When the address Ai is shifted to the high state, the output terminal (b) of a delay chain 11 shifts to the high state and MN5 is turned on in a state where the current route from the power source Vcc to ATD is interrupted and it becomes the low state. When the address Ai shifts to the low state, ATD becomes high and ATD becomes low.

97. 发明专利

JPH04229493A SEMICONDUCTOR LSI-ROM AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH04229493A
公开(公告)日：1992-08-18
申请号：JP14320691
申请日：1991-06-14
申请人： KURIEITEIBU INTEGUREITETSUDO S
发明人： JIEIMUZU EI KOMARETSUKU , SUKOTSUTO BII TAANAA , KURARENSU DABURIYUU PAJIETSUTO , JIYATSUKU ERU MINNII
IPC分类号： G11C7/06 , G11C7/10 , G11C7/12 , G11C7/22 , G11C8/06 , G11C8/10 , G11C8/18 , G11C17/12 , G11C17/18 , H01L21/8246 , H01L27/112 , H01L27/115 , H03K3/3565
摘要： PURPOSE: To provide a ROM in which malfunctions are reduced, a high speed reading is possible, and the size is reduced. CONSTITUTION: This ROM has an input buffer circuit which is useable for the LSI chip that has no noise failure and is made by the NMOS and CMOS technology, the sense circuit which compensates for the leak current of a memory element and adjusts the load in accordance with the driving signal from the memory element and an output buffer circuit having a high switching speed.

98. 发明专利

JPH04181593A SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPH04181593A
公开(公告)日：1992-06-29
申请号：JP31022290
申请日：1990-11-16
申请人： FUJITSU LTD , FUJITSU VLSI LTD
发明人： FUJII YASUHIRO , MOCHIZUKI HIROHIKO , KODAMA YUKINORI , SUGIURA AKIRA
IPC分类号： G11C11/41 , G11C8/18
摘要： PURPOSE:To enable read/write processing to be made even if an address signal with an extremely short pulse width is inputted by providing each means of column selection, information output, row selection, and address supply at a semiconductor memory device. CONSTITUTION:A memory means 14 for storing an information D, a column selection means 15 for selecting a signal line BLi in this column direction, an information output means 16 for controlling read/write of the information D, a column selection means 17 for selecting a signal line WLi in row direction of the means 14, and an address supply means 18 for supplying addresses A0 - n to the means 15 are provided and this means 18 is formed by a transition detection means 18A and an address 18B, thus enabling expansion processing to be made positively even if an address signal in a short pulse shape is inputted, an address transition detection signal in a specified pulse width to be outputted, and stability and reliability of circuit operation to be improved.

99. 发明专利

JPH04111011A INTERFACE CIRCUIT FOR SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH04111011A
公开(公告)日：1992-04-13
申请号：JP23112390
申请日：1990-08-30
申请人： MITSUBISHI ELECTRIC CORP
发明人： KIMURA MASATOSHI
IPC分类号： G06F1/26 , G06F1/18 , G06K17/00 , G11C5/14 , G11C7/22 , G11C8/18
摘要： PURPOSE:To prevent the latch-up of a semiconductor storage device and the deterioration and the breakdown caused thereby, and to safely execute the power source/bus control by optimizing the application procedure of a power source and a bus signal. CONSTITUTION:A power source control means for executing the contact/ disconnection control of a power source input line 11 in accordance with a contact signal, and a delaying means 22 for delaying the control signal are provided, and also, the control signal delayed by the delaying means 22 is applied to a bus signal control means for executing the contact/disconnection control of an input/output bus. That is, the control signal for power source contact/disconnection is delayed by the delaying means 22, and it is used for the control signal for input/output bus contact/disconnection. Accordingly, by such an optimal procedure as a bus signal is supplied to a semiconductor storage device 1 after the power source is supplied surely, the power source and the bus signal can be supplied. In such a way, latch-up of the semiconductor storage device 1 is prevented, deterioration and breakdown caused by latch-up are prevented, and the power source/bus control of the semiconductor storage device 1 can be executed safely.

100. 发明专利

JPH04109494A SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04109494A
公开(公告)日：1992-04-10
申请号：JP22866490
申请日：1990-08-30
申请人： TOSHIBA CORP , TOSHIBA MICRO ELECTRONICS , TOSBAC COMPUTER SYSTEM CO LTD
发明人： KATO HIDEO , NAKAI HIROTO , IWAHASHI HIROSHI , HIRAGA NOBUAKI
IPC分类号： G11C11/41 , G11C7/02 , G11C7/06 , G11C7/10 , G11C8/18 , G11C11/407 , G11C11/409 , G11C16/06
摘要： PURPOSE:To prevent the generation of malfunction in a data delay circuit by providing the semiconductor integrated circuit with an output buffer control circuit for setting up the output data of a data detection circuit to a state inhibiting its output from an output buffer circuit for a prescribed period based on a pulse signal outputted from an address change detecting circuit. CONSTITUTION:The data delay circuit 9 and a data latch circuit 10 are inserted between a sense amplifier circuit 7 and the output buffer circuit 8. The output buffer control circuit 11 generates a delay signal for setting up the delay time of the circuit 9 to a short value when data detected by the data detecting circuit 12 is not outputted from the circuit 8, and setting up the delay time to a longer value when data are outputted from the circuit 8. The circuit 9 is set up so as not to generate the delay signal after stopping the generation of the pulse output signal from the circuit 12. Consequently, the generation of malfunction due to power supply variation at the time of changing output data or the input of noise from the external can be prevented.

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