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    • 1. 发明专利
    • SEMICONDUCTOR MEMORY DEVICE
    • JPH06111597A
    • 1994-04-22
    • JP25505892
    • 1992-09-24
    • NEC CORP
    • ITO MUNEHIRO
    • G11C11/41G11C8/18G11C11/413G11C29/00G11C29/04
    • PURPOSE:To activate a selected redundancy address switch at high speed and to shorten address access time by using a signal of an input side of a logic circuit as a pre-charge signal of a redundancy decoder and performing pre- charge quickly. CONSTITUTION:A redundancy decoder (RD) and address buffer groups 10, 11 specifying a reading address are provided on an information reading circuit of a buffer group 13. ATD circuits A 20 and B 21 connected to these buffer groups 10, 11 detect variation of an address signal and the outputted detected output ATDA and B are integrated by a NAND gate 23. Further, a signal of an input side of a gate 23 is used as a pre-charge signal of the RD, a transistor 52 is added in parallel to a (p) type transistor 51 of ATD input, and each input is made ATDA and B of two stages before ATD. Thereby, precharge of RD is quickly performed, the selected redundancy address switches are activated at high speed and address access time is shortened.