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    • 91. 发明专利
    • Driving circuit for ignition element of safety device
    • 用于安全装置点火元件的驱动电路
    • JP2007284040A
    • 2007-11-01
    • JP2007066574
    • 2007-03-15
    • Infineon Technologies Agインフィネオン テクノロジーズ アクチエンゲゼルシャフト
    • JUST OLAFLIMMER JOSEFDITTFELD TIMO
    • B60R21/16B60R22/48
    • B60R21/017F42C15/40
    • PROBLEM TO BE SOLVED: To obtain information about the current which has flowed in an ignition element in an accident to analyze how the accident occurred after the accident. SOLUTION: The driving circuit is provided with one or more ignition element terminals 31 and 32 for connecting the ignition element 30, a controllable current or voltage source 10 connected to the one or more ignition element terminals, and a sensor section having at least one detecting element 20. The detecting element is arranged inside a current passage between the current or voltage source and the one or more ignition element terminals, or arranged adjacent to the current passage. The detecting element includes a sensor material designed to be changed in color directly or indirectly depending on the current flowing between the current or voltage source and the ignition element. COPYRIGHT: (C)2008,JPO&INPIT
    • 要解决的问题:获取有关在事故中点燃元件中流动的电流的信息,以分析事故发生后的事故。 解决方案:驱动电路设置有一个或多个用于连接点火元件30,连接到一个或多个点火元件端子的可控电流或电压源10的点火元件端子31和32,以及具有 至少一个检测元件20.检测元件布置在电流源或电压源与一个或多个点火元件端子之间的电流通道内或邻近电流通道布置。 检测元件包括被设计为根据在电流源或电压源与点火元件之间流动的电流直接或间接地改变颜色的传感器材料。 版权所有(C)2008,JPO&INPIT
    • 92. 发明专利
    • Pulsed static flip-flop
    • PULSED STATIC FLIP-FLOP
    • JP2007184925A
    • 2007-07-19
    • JP2006351993
    • 2006-12-27
    • Infineon Technologies Agインフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG
    • KEPPE SIEGMARPACHA CHRISTIANZAPF KARL
    • H03K3/356H03K3/037
    • H03K3/35625H03K3/012
    • PROBLEM TO BE SOLVED: To provide a short set-up time, in particular, to reduce generated clock edge-to-output signal delay.
      SOLUTION: The present invention relates to a pulsed static flip-flop 1 for storing a logic state of a logic signal (/D1), the flip-flop having a first logic circuit 6 which logically combines the logic signal (/D1) with a pulsed signal (PULSE) and outputs a set signal (/SET), a second logic circuit 7 which logically combines a logic input signal (/D) with a complementary pulsed signal (/PULSE) and outputs a reset signal (/RES), and a latch device 14 having a storage means 17, 18, 19 which holds a logic hold level, the hold level being controlled by the set signal (/SET), and the hold level being tapped off as a stored logic state of the logic signal (/D1).
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供短的设置时间,特别是减少产生的时钟边沿到输出信号延迟。 解决方案:本发明涉及一种用于存储逻辑信号(/ D1)的逻辑状态的脉冲静态触发器1,触发器具有逻辑组合逻辑信号(/ D1)的第一逻辑电路6 )和脉冲信号(PULSE),并输出设定信号(/ SET);第二逻辑电路7逻辑组合逻辑输入信号(/ D)与互补脉冲信号(/ PULSE),并输出复位信号(/ RES)和具有保持逻辑保持电平的存储装置17,18,19的锁存装置14,保持电平由设置信号(/ SET)控制,并且保持电平作为存储的逻辑状态被分接 的逻辑信号(/ D1)。 版权所有(C)2007,JPO&INPIT
    • 93. 发明专利
    • Analog-to-digital converter and method for converting analog signal into digital signal
    • 模拟数字转换器和将模拟信号转换为数字信号的方法
    • JP2007143185A
    • 2007-06-07
    • JP2007008553
    • 2007-01-17
    • Infineon Technologies Agインフィネオン テクノロジーズ アクチエンゲゼルシャフト
    • PAULUS CHRISTIAN
    • H03M1/10H03M1/36H03M1/06
    • H03M1/0643H03M1/365
    • PROBLEM TO BE SOLVED: To provide an analog-to-digital converter and a method for achieving high accuracy and linearity of a device, even when the magnitude of a component is small.
      SOLUTION: The present invention relates to the analog-to-digital converter (301), having several comparators (303) and to a reference circuit network. The reference circuit network comprises several reference elements (302). At least one input (304) of at least one comparator (303) is connected between the individual reference elements (302) of the reference circuit network in the analog-to-digital converter (301), respectively. A digital evaluation circuit (311), with which the statistical evaluation of output signals generated by the comparators (303) can be carried out, is linked to outputs (309) of the comparators (303) of the analog-to-digital converter (301). The present invention also relates to a method for converting an analog signal (U
      a ) into a digital signal (D).
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:即使当部件的大小小时,提供一种模数转换器和用于实现器件的高精度和线性度的方法。 解决方案:本发明涉及具有多个比较器(303)和参考电路网络的模拟 - 数字转换器(301)。 参考电路网络包括多个参考元件(302)。 至少一个比较器(303)的至少一个输入端(304)分别连接在模拟 - 数字转换器(301)中的参考电路网络的各个参考元件(302)之间。 可以执行由比较器(303)产生的输出信号的统计评估的数字评估电路(311)与模数转换器(303)的比较器(303)的输出(309)相关联 301)。 本发明还涉及一种将模拟信号(U a )转换为数字信号(D)的方法。 版权所有(C)2007,JPO&INPIT
    • 95. 发明专利
    • Formation method for semiconductor structure, and semiconductor structure corresponding to formation method
    • 半导体结构的形成方法和与形成方法相关的半导体结构
    • JP2007049121A
    • 2007-02-22
    • JP2006175042
    • 2006-06-26
    • Infineon Technologies Agインフィネオン テヒノロギーズ アーゲーInfineon TechnologiesAG
    • BIRNER ALBERTWEBER ANDREASWEIS ROLF
    • H01L21/76H01L21/8234H01L27/08H01L27/088H01L29/78
    • H01L21/76224H01L27/10873H01L29/1037
    • PROBLEM TO BE SOLVED: To provide a semiconductor structure, corresponding to a formation method for a semiconductor structure after improving the formation method, and to improve the shape of active region.
      SOLUTION: The formation method includes a step for providing a semiconductor substrate having an active region with a structure for exposing the upper side, a step for forming at least one STI trench adjacent to the active region and having an insulating filler extended to a part above the upper side of the active region, a step for forming an STI divot (adjacent to the active region and making an edge of the exposed upper side of the active region exposed) to the insulating filler, a step for forming a hydrogen termination region to the exposed upper side of the active region, and a step for forming a round part (KV; KV') to the edge of the active region so that the upper side of the active region is continuously connected to the STI divot, while executing heat treatment in a hydrogen atmosphere.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供一种半导体结构,其对应于在改善形成方法之后的半导体结构的形成方法,并且改善有源区的形状。 解决方案:所述形成方法包括提供具有具有用于暴露上侧的结构的有源区的半导体衬底的步骤,用于形成邻近有源区的至少一个STI沟槽并具有延伸到 在有源区的上侧上方的部分,用于形成STI绝缘体(与有源区相邻并使暴露的有源区的暴露上侧的边缘)暴露于绝缘填料的步骤,形成氢 终止区域到有源区域的暴露的上侧;以及用于向有源区域的边缘形成圆形部分(KV; KV')的步骤,使得有源区域的上侧连续地连接到STI纹路, 同时在氢气氛中进行热处理。 版权所有(C)2007,JPO&INPIT
    • 96. 发明专利
    • Digital/analog converter and method of digital/analog conversion of signals
    • 数字/模拟转换器和数字/模拟转换信号的方法
    • JP2007037156A
    • 2007-02-08
    • JP2006206757
    • 2006-07-28
    • Infineon Technologies Agインフィネオン テクノロジーズ アクチエンゲゼルシャフト
    • SCHWOERER CHRISTOPH
    • H03M3/02
    • H03H11/12H03H11/1286H03M3/344H03M3/502H03M7/3022
    • PROBLEM TO BE SOLVED: To eliminate noises and improve responses by filtering signals output by a noise shaper.
      SOLUTION: The digital/analog converter is equipped with an input part 11 for supplying a first digital word having a first word length. A noise shaper 1, connected with the converter converts the first digital word to a second digital word having a second word length, and outputs it. The output part of the noise shaper 1 is connected to a filter part 2 provided to remove signal components in the second digital word. Finally, a digital/analog converting part 3 is connected to output parts 24, 25 and 26 of the filter part 2, converts the second digital word into an analog signal and supplies the analog signal to an output part 40. By filtering the signal output by using the noise shaper, noise components in the second digital word which has undergone noise formation are removed.
      COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:通过对由噪声整形器输出的信号进行滤波来消除噪声并改善响应。 解决方案:数字/模拟转换器配备有用于提供具有第一字长的第一数字字的输入部分11。 与转换器连接的噪声整形器1将第一数字字转换为具有第二字长的第二数字字,并将其输出。 噪声整形器1的输出部分连接到滤波器部分2,滤波器部分2用于去除第二数字字中的信号分量。 最后,数字/模拟转换部分3连接到滤波器部分2的输出部分24,25和26,将第二数字字转换为模拟信号,并将模拟信号提供给输出部分40.通过对信号输出进行滤波 通过使用噪声整形器,去除已经经历噪声形成的第二数字字中的噪声分量。 版权所有(C)2007,JPO&INPIT
    • 97. 发明专利
    • Direct channel stress
    • 直接通道应力
    • JP2007027747A
    • 2007-02-01
    • JP2006193321
    • 2006-07-13
    • Infineon Technologies Agインフィネオン テクノロジーズ アクチエンゲゼルシャフト
    • KNOEFLER ROMANTILKE ARMIN
    • H01L21/20H01L21/336H01L21/8238H01L27/092H01L29/78H01L29/786
    • H01L21/823807H01L21/26506H01L29/7833H01L29/7848
    • PROBLEM TO BE SOLVED: To provide a MOS transistor with improved mobility. SOLUTION: A step of forming a tensile channel region in a semiconductor device is included. In one form, a step of straining a stress layer covering an amorphous portion of the semiconductor device in the intermediate stage of manufacture is included. The semiconductor device is masked, and the strain in a part of the stress layer is relaxed. The strain from the stress layer is conveyed to the substrate by recrystallizing the amorphous portion of the semiconductor device in the middle of manufacture. At least a part of strain remains on the substrate during the manufacturing step of the device. Consequently, the performance of the completed device can be improved. In the other form, the tensile stress layer is formed to cover the first portion of the device, and the compressive stress layer is formed to cover the second portion of the device. The tensile stress layer forms the compressive channel in a PMOS device, and the compressive stress layer forms the tensile channel in an NMOS device. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供具有改善的移动性的MOS晶体管。 解决方案:包括在半导体器件中形成拉伸沟道区的步骤。 在一种形式中,包括在制造的中间阶段使覆盖半导体器件的非晶部分的应力层变形的步骤。 半导体器件被掩蔽,应力层的一部分中的应变被放宽。 来自应力层的应变通过在制造中间重结晶半导体器件的非晶部分被输送到基板。 在器件的制造步骤期间,至少一部分应变残留在衬底上。 因此,可以提高完成的装置的性能。 在另一种形式中,形成拉伸应力层以覆盖器件的第一部分,并且形成压应力层以覆盖器件的第二部分。 拉伸应力层在PMOS器件中形成压缩通道,并且压应力层在NMOS器件中形成拉伸通道。 版权所有(C)2007,JPO&INPIT
    • 100. 发明专利
    • Integrated circuit having inductor in multilayer conductive layer
    • 在多层导电层中具有电感器的集成电路
    • JP2007005798A
    • 2007-01-11
    • JP2006169520
    • 2006-06-20
    • Infineon Technologies Agインフィネオン テクノロジーズ アクチエンゲゼルシャフト
    • BAUMGARTNER PETERBENETIK THOMAS
    • H01L21/822H01L27/04
    • H01F17/0006H01F2021/125
    • PROBLEM TO BE SOLVED: To provide a semiconductor device capable of improving a symmetry of a differential inductor, and enhancing a performance thereof. SOLUTION: In a multilayer conductive layer of an integrated circuit, the symmetry part of a first inductor and a second inductor is formed in two or more conductive layers. The respective first inductors provided in adjacent conductive layers or the respective second inductors provided in the adjacent conductive layers are mutually connected by via. An approximately a loop structure is formed in each conductive layer by the first and second inductor parts. The first and second inductor vias may be disposed at the same position in the approximately looped inductor structure by exchanging an inner radius and an outer radius. Alternately, by using a notch in the first and second inductors, the first and second inductor vias may be disposed, so that the via for the second inductor is disposed on the opposite side of the via for the first inductor in the approximately looped inductor structure. COPYRIGHT: (C)2007,JPO&INPIT
    • 要解决的问题:提供能够提高差分电感器的对称性并提高其性能的半导体器件。 解决方案:在集成电路的多层导电层中,第一电感器和第二电感器的对称部分形成在两个或更多个导电层中。 设置在相邻导电层中的相应的第一电感器或设置在相邻的导电层中的相应的第二电感器通过通孔相互连接。 通过第一和第二电感器部件在每个导电层中形成大致环形结构。 第一和第二电感器通孔可以通过交换内半径和外半径而设置在近环形电感器结构中的相同位置处。 或者,通过使用第一和第二电感器中的陷波,可以设置第一和第二电感器通孔,使得用于第二电感器的通孔设置在大致环形的电感器结构中用于第一电感器的通路的相对侧 。 版权所有(C)2007,JPO&INPIT